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-rw-r--r--src/wasm/wasm-binary.cpp24
-rw-r--r--src/wasm/wasm-s-parser.cpp9
-rw-r--r--src/wasm/wasm-stack.cpp13
-rw-r--r--src/wasm/wasm.cpp5
4 files changed, 51 insertions, 0 deletions
diff --git a/src/wasm/wasm-binary.cpp b/src/wasm/wasm-binary.cpp
index b7ffcd8d7..2c473a254 100644
--- a/src/wasm/wasm-binary.cpp
+++ b/src/wasm/wasm-binary.cpp
@@ -3005,6 +3005,9 @@ BinaryConsts::ASTNodes WasmBinaryBuilder::readExpression(Expression*& curr) {
if (maybeVisitSIMDLoadStoreLane(curr, opcode)) {
break;
}
+ if (maybeVisitSIMDWiden(curr, opcode)) {
+ break;
+ }
if (maybeVisitPrefetch(curr, opcode)) {
break;
}
@@ -5466,6 +5469,27 @@ bool WasmBinaryBuilder::maybeVisitSIMDLoadStoreLane(Expression*& out,
return true;
}
+bool WasmBinaryBuilder::maybeVisitSIMDWiden(Expression*& out, uint32_t code) {
+ SIMDWidenOp op;
+ switch (code) {
+ case BinaryConsts::I32x4WidenSI8x16:
+ op = WidenSVecI8x16ToVecI32x4;
+ break;
+ case BinaryConsts::I32x4WidenUI8x16:
+ op = WidenUVecI8x16ToVecI32x4;
+ break;
+ default:
+ return false;
+ }
+ auto* curr = allocator.alloc<SIMDWiden>();
+ curr->op = op;
+ curr->index = getLaneIndex(4);
+ curr->vec = popNonVoidExpression();
+ curr->finalize();
+ out = curr;
+ return true;
+}
+
bool WasmBinaryBuilder::maybeVisitPrefetch(Expression*& out, uint32_t code) {
PrefetchOp op;
switch (code) {
diff --git a/src/wasm/wasm-s-parser.cpp b/src/wasm/wasm-s-parser.cpp
index 3075f70d7..0dc121f2c 100644
--- a/src/wasm/wasm-s-parser.cpp
+++ b/src/wasm/wasm-s-parser.cpp
@@ -1666,6 +1666,15 @@ SExpressionWasmBuilder::makeSIMDLoadStoreLane(Element& s,
return ret;
}
+Expression* SExpressionWasmBuilder::makeSIMDWiden(Element& s, SIMDWidenOp op) {
+ auto* ret = allocator.alloc<SIMDWiden>();
+ ret->op = op;
+ ret->index = parseLaneIndex(s[1], 4);
+ ret->vec = parseExpression(s[2]);
+ ret->finalize();
+ return ret;
+}
+
Expression* SExpressionWasmBuilder::makePrefetch(Element& s, PrefetchOp op) {
Address offset, align;
size_t i = parseMemAttributes(s, offset, align, /*defaultAlign*/ 1);
diff --git a/src/wasm/wasm-stack.cpp b/src/wasm/wasm-stack.cpp
index d42080bac..cb8702d0c 100644
--- a/src/wasm/wasm-stack.cpp
+++ b/src/wasm/wasm-stack.cpp
@@ -691,6 +691,19 @@ void BinaryInstWriter::visitSIMDLoadStoreLane(SIMDLoadStoreLane* curr) {
o << curr->index;
}
+void BinaryInstWriter::visitSIMDWiden(SIMDWiden* curr) {
+ o << int8_t(BinaryConsts::SIMDPrefix);
+ switch (curr->op) {
+ case WidenSVecI8x16ToVecI32x4:
+ o << U32LEB(BinaryConsts::I32x4WidenSI8x16);
+ break;
+ case WidenUVecI8x16ToVecI32x4:
+ o << U32LEB(BinaryConsts::I32x4WidenUI8x16);
+ break;
+ }
+ o << uint8_t(curr->index);
+}
+
void BinaryInstWriter::visitPrefetch(Prefetch* curr) {
o << int8_t(BinaryConsts::SIMDPrefix);
switch (curr->op) {
diff --git a/src/wasm/wasm.cpp b/src/wasm/wasm.cpp
index f8d8890ec..e9d2bf116 100644
--- a/src/wasm/wasm.cpp
+++ b/src/wasm/wasm.cpp
@@ -496,6 +496,11 @@ void SIMDLoadStoreLane::finalize() {
}
}
+void SIMDWiden::finalize() {
+ assert(vec);
+ type = vec->type == Type::unreachable ? Type::unreachable : Type::v128;
+}
+
Index SIMDLoadStoreLane::getMemBytes() {
switch (op) {
case LoadLaneVec8x16: