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-rw-r--r--src/binaryen-c.cpp24
-rw-r--r--src/binaryen-c.h12
-rw-r--r--src/gen-s-parser.inc12
-rw-r--r--src/js/binaryen.js-post.js24
-rw-r--r--src/passes/Print.cpp12
-rw-r--r--src/tools/fuzzing.h24
-rw-r--r--src/wasm-interpreter.h36
-rw-r--r--src/wasm.h12
-rw-r--r--src/wasm/wasm-binary.cpp12
-rw-r--r--src/wasm/wasm-s-parser.cpp12
-rw-r--r--src/wasm/wasm-stack.cpp12
-rw-r--r--src/wasm/wasm-validator.cpp12
-rw-r--r--src/wasm/wasm.cpp12
13 files changed, 102 insertions, 114 deletions
diff --git a/src/binaryen-c.cpp b/src/binaryen-c.cpp
index a644721d8..161dcf9e3 100644
--- a/src/binaryen-c.cpp
+++ b/src/binaryen-c.cpp
@@ -669,24 +669,12 @@ BinaryenOp BinaryenLoad8SplatVec128(void) { return Load8SplatVec128; }
BinaryenOp BinaryenLoad16SplatVec128(void) { return Load16SplatVec128; }
BinaryenOp BinaryenLoad32SplatVec128(void) { return Load32SplatVec128; }
BinaryenOp BinaryenLoad64SplatVec128(void) { return Load64SplatVec128; }
-BinaryenOp BinaryenLoadExtSVec8x8ToVecI16x8(void) {
- return LoadExtSVec8x8ToVecI16x8;
-}
-BinaryenOp BinaryenLoadExtUVec8x8ToVecI16x8(void) {
- return LoadExtUVec8x8ToVecI16x8;
-}
-BinaryenOp BinaryenLoadExtSVec16x4ToVecI32x4(void) {
- return LoadExtSVec16x4ToVecI32x4;
-}
-BinaryenOp BinaryenLoadExtUVec16x4ToVecI32x4(void) {
- return LoadExtUVec16x4ToVecI32x4;
-}
-BinaryenOp BinaryenLoadExtSVec32x2ToVecI64x2(void) {
- return LoadExtSVec32x2ToVecI64x2;
-}
-BinaryenOp BinaryenLoadExtUVec32x2ToVecI64x2(void) {
- return LoadExtUVec32x2ToVecI64x2;
-}
+BinaryenOp BinaryenLoad8x8SVec128(void) { return Load8x8SVec128; }
+BinaryenOp BinaryenLoad8x8UVec128(void) { return Load8x8UVec128; }
+BinaryenOp BinaryenLoad16x4SVec128(void) { return Load16x4SVec128; }
+BinaryenOp BinaryenLoad16x4UVec128(void) { return Load16x4UVec128; }
+BinaryenOp BinaryenLoad32x2SVec128(void) { return Load32x2SVec128; }
+BinaryenOp BinaryenLoad32x2UVec128(void) { return Load32x2UVec128; }
BinaryenOp BinaryenLoad32ZeroVec128(void) { return Load32ZeroVec128; }
BinaryenOp BinaryenLoad64ZeroVec128(void) { return Load64ZeroVec128; }
BinaryenOp BinaryenLoad8LaneVec128(void) { return Load8LaneVec128; }
diff --git a/src/binaryen-c.h b/src/binaryen-c.h
index 06cfaa08e..47d255749 100644
--- a/src/binaryen-c.h
+++ b/src/binaryen-c.h
@@ -552,12 +552,12 @@ BINARYEN_API BinaryenOp BinaryenLoad8SplatVec128(void);
BINARYEN_API BinaryenOp BinaryenLoad16SplatVec128(void);
BINARYEN_API BinaryenOp BinaryenLoad32SplatVec128(void);
BINARYEN_API BinaryenOp BinaryenLoad64SplatVec128(void);
-BINARYEN_API BinaryenOp BinaryenLoadExtSVec8x8ToVecI16x8(void);
-BINARYEN_API BinaryenOp BinaryenLoadExtUVec8x8ToVecI16x8(void);
-BINARYEN_API BinaryenOp BinaryenLoadExtSVec16x4ToVecI32x4(void);
-BINARYEN_API BinaryenOp BinaryenLoadExtUVec16x4ToVecI32x4(void);
-BINARYEN_API BinaryenOp BinaryenLoadExtSVec32x2ToVecI64x2(void);
-BINARYEN_API BinaryenOp BinaryenLoadExtUVec32x2ToVecI64x2(void);
+BINARYEN_API BinaryenOp BinaryenLoad8x8SVec128(void);
+BINARYEN_API BinaryenOp BinaryenLoad8x8UVec128(void);
+BINARYEN_API BinaryenOp BinaryenLoad16x4SVec128(void);
+BINARYEN_API BinaryenOp BinaryenLoad16x4UVec128(void);
+BINARYEN_API BinaryenOp BinaryenLoad32x2SVec128(void);
+BINARYEN_API BinaryenOp BinaryenLoad32x2UVec128(void);
BINARYEN_API BinaryenOp BinaryenLoad32ZeroVec128(void);
BINARYEN_API BinaryenOp BinaryenLoad64ZeroVec128(void);
BINARYEN_API BinaryenOp BinaryenLoad8LaneVec128(void);
diff --git a/src/gen-s-parser.inc b/src/gen-s-parser.inc
index 88d7f15a1..73e3cf861 100644
--- a/src/gen-s-parser.inc
+++ b/src/gen-s-parser.inc
@@ -3009,10 +3009,10 @@ switch (op[0]) {
case 'x': {
switch (op[14]) {
case 's':
- if (strcmp(op, "v128.load16x4_s") == 0) { return makeSIMDLoad(s, SIMDLoadOp::LoadExtSVec16x4ToVecI32x4); }
+ if (strcmp(op, "v128.load16x4_s") == 0) { return makeSIMDLoad(s, SIMDLoadOp::Load16x4SVec128); }
goto parse_error;
case 'u':
- if (strcmp(op, "v128.load16x4_u") == 0) { return makeSIMDLoad(s, SIMDLoadOp::LoadExtUVec16x4ToVecI32x4); }
+ if (strcmp(op, "v128.load16x4_u") == 0) { return makeSIMDLoad(s, SIMDLoadOp::Load16x4UVec128); }
goto parse_error;
default: goto parse_error;
}
@@ -3039,10 +3039,10 @@ switch (op[0]) {
case 'x': {
switch (op[14]) {
case 's':
- if (strcmp(op, "v128.load32x2_s") == 0) { return makeSIMDLoad(s, SIMDLoadOp::LoadExtSVec32x2ToVecI64x2); }
+ if (strcmp(op, "v128.load32x2_s") == 0) { return makeSIMDLoad(s, SIMDLoadOp::Load32x2SVec128); }
goto parse_error;
case 'u':
- if (strcmp(op, "v128.load32x2_u") == 0) { return makeSIMDLoad(s, SIMDLoadOp::LoadExtUVec32x2ToVecI64x2); }
+ if (strcmp(op, "v128.load32x2_u") == 0) { return makeSIMDLoad(s, SIMDLoadOp::Load32x2UVec128); }
goto parse_error;
default: goto parse_error;
}
@@ -3080,10 +3080,10 @@ switch (op[0]) {
case 'x': {
switch (op[13]) {
case 's':
- if (strcmp(op, "v128.load8x8_s") == 0) { return makeSIMDLoad(s, SIMDLoadOp::LoadExtSVec8x8ToVecI16x8); }
+ if (strcmp(op, "v128.load8x8_s") == 0) { return makeSIMDLoad(s, SIMDLoadOp::Load8x8SVec128); }
goto parse_error;
case 'u':
- if (strcmp(op, "v128.load8x8_u") == 0) { return makeSIMDLoad(s, SIMDLoadOp::LoadExtUVec8x8ToVecI16x8); }
+ if (strcmp(op, "v128.load8x8_u") == 0) { return makeSIMDLoad(s, SIMDLoadOp::Load8x8UVec128); }
goto parse_error;
default: goto parse_error;
}
diff --git a/src/js/binaryen.js-post.js b/src/js/binaryen.js-post.js
index 584c6b7d8..96dad5e7b 100644
--- a/src/js/binaryen.js-post.js
+++ b/src/js/binaryen.js-post.js
@@ -484,12 +484,12 @@ function initializeConstants() {
'Load16SplatVec128',
'Load32SplatVec128',
'Load64SplatVec128',
- 'LoadExtSVec8x8ToVecI16x8',
- 'LoadExtUVec8x8ToVecI16x8',
- 'LoadExtSVec16x4ToVecI32x4',
- 'LoadExtUVec16x4ToVecI32x4',
- 'LoadExtSVec32x2ToVecI64x2',
- 'LoadExtUVec32x2ToVecI64x2',
+ 'Load8x8SVec128',
+ 'Load8x8UVec128',
+ 'Load16x4SVec128',
+ 'Load16x4UVec128',
+ 'Load32x2SVec128',
+ 'Load32x2UVec128',
'Load32ZeroVec128',
'Load64ZeroVec128',
'Load8LaneVec128',
@@ -1483,22 +1483,22 @@ function wrapModule(module, self = {}) {
return Module['_BinaryenSIMDLoad'](module, Module['Load64SplatVec128'], offset, align, ptr);
},
'load8x8_s'(offset, align, ptr) {
- return Module['_BinaryenSIMDLoad'](module, Module['LoadExtSVec8x8ToVecI16x8'], offset, align, ptr);
+ return Module['_BinaryenSIMDLoad'](module, Module['Load8x8SVec128'], offset, align, ptr);
},
'load8x8_u'(offset, align, ptr) {
- return Module['_BinaryenSIMDLoad'](module, Module['LoadExtUVec8x8ToVecI16x8'], offset, align, ptr);
+ return Module['_BinaryenSIMDLoad'](module, Module['Load8x8UVec128'], offset, align, ptr);
},
'load16x4_s'(offset, align, ptr) {
- return Module['_BinaryenSIMDLoad'](module, Module['LoadExtSVec16x4ToVecI32x4'], offset, align, ptr);
+ return Module['_BinaryenSIMDLoad'](module, Module['Load16x4SVec128'], offset, align, ptr);
},
'load16x4_u'(offset, align, ptr) {
- return Module['_BinaryenSIMDLoad'](module, Module['LoadExtUVec16x4ToVecI32x4'], offset, align, ptr);
+ return Module['_BinaryenSIMDLoad'](module, Module['Load16x4UVec128'], offset, align, ptr);
},
'load32x2_s'(offset, align, ptr) {
- return Module['_BinaryenSIMDLoad'](module, Module['LoadExtSVec32x2ToVecI64x2'], offset, align, ptr);
+ return Module['_BinaryenSIMDLoad'](module, Module['Load32x2SVec128'], offset, align, ptr);
},
'load32x2_u'(offset, align, ptr) {
- return Module['_BinaryenSIMDLoad'](module, Module['LoadExtUVec32x2ToVecI64x2'], offset, align, ptr);
+ return Module['_BinaryenSIMDLoad'](module, Module['Load32x2UVec128'], offset, align, ptr);
},
'load32_zero'(offset, align, ptr) {
return Module['_BinaryenSIMDLoad'](module, Module['Load32ZeroVec128'], offset, align, ptr);
diff --git a/src/passes/Print.cpp b/src/passes/Print.cpp
index 310d59275..fa61a3d1c 100644
--- a/src/passes/Print.cpp
+++ b/src/passes/Print.cpp
@@ -711,22 +711,22 @@ struct PrintExpressionContents
case Load64SplatVec128:
o << "v128.load64_splat";
break;
- case LoadExtSVec8x8ToVecI16x8:
+ case Load8x8SVec128:
o << "v128.load8x8_s";
break;
- case LoadExtUVec8x8ToVecI16x8:
+ case Load8x8UVec128:
o << "v128.load8x8_u";
break;
- case LoadExtSVec16x4ToVecI32x4:
+ case Load16x4SVec128:
o << "v128.load16x4_s";
break;
- case LoadExtUVec16x4ToVecI32x4:
+ case Load16x4UVec128:
o << "v128.load16x4_u";
break;
- case LoadExtSVec32x2ToVecI64x2:
+ case Load32x2SVec128:
o << "v128.load32x2_s";
break;
- case LoadExtUVec32x2ToVecI64x2:
+ case Load32x2UVec128:
o << "v128.load32x2_u";
break;
case Load32ZeroVec128:
diff --git a/src/tools/fuzzing.h b/src/tools/fuzzing.h
index 183347c70..8dd083391 100644
--- a/src/tools/fuzzing.h
+++ b/src/tools/fuzzing.h
@@ -2950,12 +2950,12 @@ private:
Load16SplatVec128,
Load32SplatVec128,
Load64SplatVec128,
- LoadExtSVec8x8ToVecI16x8,
- LoadExtUVec8x8ToVecI16x8,
- LoadExtSVec16x4ToVecI32x4,
- LoadExtUVec16x4ToVecI32x4,
- LoadExtSVec32x2ToVecI64x2,
- LoadExtUVec32x2ToVecI64x2);
+ Load8x8SVec128,
+ Load8x8UVec128,
+ Load16x4SVec128,
+ Load16x4UVec128,
+ Load32x2SVec128,
+ Load32x2UVec128);
Address offset = logify(get());
Address align;
switch (op) {
@@ -2969,12 +2969,12 @@ private:
align = pick(1, 2, 4);
break;
case Load64SplatVec128:
- case LoadExtSVec8x8ToVecI16x8:
- case LoadExtUVec8x8ToVecI16x8:
- case LoadExtSVec16x4ToVecI32x4:
- case LoadExtUVec16x4ToVecI32x4:
- case LoadExtSVec32x2ToVecI64x2:
- case LoadExtUVec32x2ToVecI64x2:
+ case Load8x8SVec128:
+ case Load8x8UVec128:
+ case Load16x4SVec128:
+ case Load16x4UVec128:
+ case Load32x2SVec128:
+ case Load32x2UVec128:
align = pick(1, 2, 4, 8);
break;
case Load32ZeroVec128:
diff --git a/src/wasm-interpreter.h b/src/wasm-interpreter.h
index bb6361321..d76f3fabf 100644
--- a/src/wasm-interpreter.h
+++ b/src/wasm-interpreter.h
@@ -2686,12 +2686,12 @@ private:
case Load32SplatVec128:
case Load64SplatVec128:
return visitSIMDLoadSplat(curr);
- case LoadExtSVec8x8ToVecI16x8:
- case LoadExtUVec8x8ToVecI16x8:
- case LoadExtSVec16x4ToVecI32x4:
- case LoadExtUVec16x4ToVecI32x4:
- case LoadExtSVec32x2ToVecI64x2:
- case LoadExtUVec32x2ToVecI64x2:
+ case Load8x8SVec128:
+ case Load8x8UVec128:
+ case Load16x4SVec128:
+ case Load16x4UVec128:
+ case Load32x2SVec128:
+ case Load32x2UVec128:
return visitSIMDLoadExtend(curr);
case Load32ZeroVec128:
case Load64ZeroVec128:
@@ -2742,17 +2742,17 @@ private:
Address src(uint32_t(flow.getSingleValue().geti32()));
auto loadLane = [&](Address addr) {
switch (curr->op) {
- case LoadExtSVec8x8ToVecI16x8:
+ case Load8x8SVec128:
return Literal(int32_t(instance.externalInterface->load8s(addr)));
- case LoadExtUVec8x8ToVecI16x8:
+ case Load8x8UVec128:
return Literal(int32_t(instance.externalInterface->load8u(addr)));
- case LoadExtSVec16x4ToVecI32x4:
+ case Load16x4SVec128:
return Literal(int32_t(instance.externalInterface->load16s(addr)));
- case LoadExtUVec16x4ToVecI32x4:
+ case Load16x4UVec128:
return Literal(int32_t(instance.externalInterface->load16u(addr)));
- case LoadExtSVec32x2ToVecI64x2:
+ case Load32x2SVec128:
return Literal(int64_t(instance.externalInterface->load32s(addr)));
- case LoadExtUVec32x2ToVecI64x2:
+ case Load32x2UVec128:
return Literal(int64_t(instance.externalInterface->load32u(addr)));
default:
WASM_UNREACHABLE("unexpected op");
@@ -2768,18 +2768,18 @@ private:
return Literal(lanes);
};
switch (curr->op) {
- case LoadExtSVec8x8ToVecI16x8:
- case LoadExtUVec8x8ToVecI16x8: {
+ case Load8x8SVec128:
+ case Load8x8UVec128: {
std::array<Literal, 8> lanes;
return fillLanes(lanes, 1);
}
- case LoadExtSVec16x4ToVecI32x4:
- case LoadExtUVec16x4ToVecI32x4: {
+ case Load16x4SVec128:
+ case Load16x4UVec128: {
std::array<Literal, 4> lanes;
return fillLanes(lanes, 2);
}
- case LoadExtSVec32x2ToVecI64x2:
- case LoadExtUVec32x2ToVecI64x2: {
+ case Load32x2SVec128:
+ case Load32x2UVec128: {
std::array<Literal, 2> lanes;
return fillLanes(lanes, 4);
}
diff --git a/src/wasm.h b/src/wasm.h
index 24162dca4..7e692bb96 100644
--- a/src/wasm.h
+++ b/src/wasm.h
@@ -504,12 +504,12 @@ enum SIMDLoadOp {
Load16SplatVec128,
Load32SplatVec128,
Load64SplatVec128,
- LoadExtSVec8x8ToVecI16x8,
- LoadExtUVec8x8ToVecI16x8,
- LoadExtSVec16x4ToVecI32x4,
- LoadExtUVec16x4ToVecI32x4,
- LoadExtSVec32x2ToVecI64x2,
- LoadExtUVec32x2ToVecI64x2,
+ Load8x8SVec128,
+ Load8x8UVec128,
+ Load16x4SVec128,
+ Load16x4UVec128,
+ Load32x2SVec128,
+ Load32x2UVec128,
Load32ZeroVec128,
Load64ZeroVec128,
};
diff --git a/src/wasm/wasm-binary.cpp b/src/wasm/wasm-binary.cpp
index 4ca434bdf..b7a04a324 100644
--- a/src/wasm/wasm-binary.cpp
+++ b/src/wasm/wasm-binary.cpp
@@ -5850,27 +5850,27 @@ bool WasmBinaryBuilder::maybeVisitSIMDLoad(Expression*& out, uint32_t code) {
break;
case BinaryConsts::V128Load8x8S:
curr = allocator.alloc<SIMDLoad>();
- curr->op = LoadExtSVec8x8ToVecI16x8;
+ curr->op = Load8x8SVec128;
break;
case BinaryConsts::V128Load8x8U:
curr = allocator.alloc<SIMDLoad>();
- curr->op = LoadExtUVec8x8ToVecI16x8;
+ curr->op = Load8x8UVec128;
break;
case BinaryConsts::V128Load16x4S:
curr = allocator.alloc<SIMDLoad>();
- curr->op = LoadExtSVec16x4ToVecI32x4;
+ curr->op = Load16x4SVec128;
break;
case BinaryConsts::V128Load16x4U:
curr = allocator.alloc<SIMDLoad>();
- curr->op = LoadExtUVec16x4ToVecI32x4;
+ curr->op = Load16x4UVec128;
break;
case BinaryConsts::V128Load32x2S:
curr = allocator.alloc<SIMDLoad>();
- curr->op = LoadExtSVec32x2ToVecI64x2;
+ curr->op = Load32x2SVec128;
break;
case BinaryConsts::V128Load32x2U:
curr = allocator.alloc<SIMDLoad>();
- curr->op = LoadExtUVec32x2ToVecI64x2;
+ curr->op = Load32x2UVec128;
break;
case BinaryConsts::V128Load32Zero:
curr = allocator.alloc<SIMDLoad>();
diff --git a/src/wasm/wasm-s-parser.cpp b/src/wasm/wasm-s-parser.cpp
index 93c22c502..9f7a2af12 100644
--- a/src/wasm/wasm-s-parser.cpp
+++ b/src/wasm/wasm-s-parser.cpp
@@ -2043,12 +2043,12 @@ Expression* SExpressionWasmBuilder::makeSIMDLoad(Element& s, SIMDLoadOp op) {
defaultAlign = 4;
break;
case Load64SplatVec128:
- case LoadExtSVec8x8ToVecI16x8:
- case LoadExtUVec8x8ToVecI16x8:
- case LoadExtSVec16x4ToVecI32x4:
- case LoadExtUVec16x4ToVecI32x4:
- case LoadExtSVec32x2ToVecI64x2:
- case LoadExtUVec32x2ToVecI64x2:
+ case Load8x8SVec128:
+ case Load8x8UVec128:
+ case Load16x4SVec128:
+ case Load16x4UVec128:
+ case Load32x2SVec128:
+ case Load32x2UVec128:
case Load64ZeroVec128:
defaultAlign = 8;
break;
diff --git a/src/wasm/wasm-stack.cpp b/src/wasm/wasm-stack.cpp
index 1b56c1389..ab38d5275 100644
--- a/src/wasm/wasm-stack.cpp
+++ b/src/wasm/wasm-stack.cpp
@@ -606,22 +606,22 @@ void BinaryInstWriter::visitSIMDLoad(SIMDLoad* curr) {
case Load64SplatVec128:
o << U32LEB(BinaryConsts::V128Load64Splat);
break;
- case LoadExtSVec8x8ToVecI16x8:
+ case Load8x8SVec128:
o << U32LEB(BinaryConsts::V128Load8x8S);
break;
- case LoadExtUVec8x8ToVecI16x8:
+ case Load8x8UVec128:
o << U32LEB(BinaryConsts::V128Load8x8U);
break;
- case LoadExtSVec16x4ToVecI32x4:
+ case Load16x4SVec128:
o << U32LEB(BinaryConsts::V128Load16x4S);
break;
- case LoadExtUVec16x4ToVecI32x4:
+ case Load16x4UVec128:
o << U32LEB(BinaryConsts::V128Load16x4U);
break;
- case LoadExtSVec32x2ToVecI64x2:
+ case Load32x2SVec128:
o << U32LEB(BinaryConsts::V128Load32x2S);
break;
- case LoadExtUVec32x2ToVecI64x2:
+ case Load32x2UVec128:
o << U32LEB(BinaryConsts::V128Load32x2U);
break;
case Load32ZeroVec128:
diff --git a/src/wasm/wasm-validator.cpp b/src/wasm/wasm-validator.cpp
index 2b5a29a9d..3079ad0bb 100644
--- a/src/wasm/wasm-validator.cpp
+++ b/src/wasm/wasm-validator.cpp
@@ -1197,12 +1197,12 @@ void FunctionValidator::visitSIMDLoad(SIMDLoad* curr) {
memAlignType = Type::i32;
break;
case Load64SplatVec128:
- case LoadExtSVec8x8ToVecI16x8:
- case LoadExtUVec8x8ToVecI16x8:
- case LoadExtSVec16x4ToVecI32x4:
- case LoadExtUVec16x4ToVecI32x4:
- case LoadExtSVec32x2ToVecI64x2:
- case LoadExtUVec32x2ToVecI64x2:
+ case Load8x8SVec128:
+ case Load8x8UVec128:
+ case Load16x4SVec128:
+ case Load16x4UVec128:
+ case Load32x2SVec128:
+ case Load32x2UVec128:
case Load64ZeroVec128:
memAlignType = Type::i64;
break;
diff --git a/src/wasm/wasm.cpp b/src/wasm/wasm.cpp
index a05cd21a0..1380b3b48 100644
--- a/src/wasm/wasm.cpp
+++ b/src/wasm/wasm.cpp
@@ -479,12 +479,12 @@ Index SIMDLoad::getMemBytes() {
case Load32ZeroVec128:
return 4;
case Load64SplatVec128:
- case LoadExtSVec8x8ToVecI16x8:
- case LoadExtUVec8x8ToVecI16x8:
- case LoadExtSVec16x4ToVecI32x4:
- case LoadExtUVec16x4ToVecI32x4:
- case LoadExtSVec32x2ToVecI64x2:
- case LoadExtUVec32x2ToVecI64x2:
+ case Load8x8SVec128:
+ case Load8x8UVec128:
+ case Load16x4SVec128:
+ case Load16x4UVec128:
+ case Load32x2SVec128:
+ case Load32x2UVec128:
case Load64ZeroVec128:
return 8;
}
generated by cgit v1.2.3 (git 2.39.1) at 2025-08-04 19:42:56 +0000