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authorWilson Snyder <wsnyder@wsnyder.org>2015-08-16 08:44:16 -0400
committerWilson Snyder <wsnyder@wsnyder.org>2015-08-16 08:44:16 -0400
commit6bfde469c6f4f7d9bcda329f3d72140bba8dce33 (patch)
treeaf132c3d550ea29c151695e01ecaaa7a35e2ff4c /lisp/emacs-lisp/cl-generic.el
parent87c4e2a686ff8b166974ca21d46faf5e802fb1b6 (diff)
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Update verilog-mode.el to 2015-05-14-6232468-vpo-GNU.
* losp/progmodes/verilog-mode.el: Fix some non-automated indent issues and comments, bug943. (verilog-type-font-keywords): Cycle delay operators like ##1 and ##[0:$] are now highlighted in their entirety similarly to the # delay-control operator. Likewise, the followed-by operators #-# and #=# are no longer partially highlighed. (verilog-backward-syntactic-ws-quick, verilog-skip-backward-comments): Minor performance improvements to buffer traversal functions for reduced latency. (verilog-calc-1, verilog-in-deferred-immediate-final-p): When the keyword 'final' follows 'assert/assume/cover', then it is part of a deferred immediate assertion item and should not be treated as a final construct for indentation. Reported by Yuri Sugihara. (verilog-do-indent): Virtual task/function/class definition lines should not be considered as declarations. Reported by Enzo Chi. (verilog-do-indent): Do not falsely indent to '=' of property/sequence operators on subsequent lines of a multi-line statement. (verilog-assignment-operator-re): Fix '!==' operator and add support for '<->', ':/', '#-#', and '#=#' operators. (verilog-calculate-indent, verilog-label-be): Enable case-sensitive regular expression parsing when looking for keywords. (verilog-calc-1): Detect 'pure virtual method' declarations which exist in abstract classes. Reported by Enzo Chi and Kaushal Modi. (verilog-backward-ws&directives): When moving back to the start of a line and the preceeding line ended with an escaped-newline, then jump up one line. This properly consumes a multi-line pre-processor directive. Reported by Kaushal Modi. (verilog-dpi-import-export-re, verilog-extended-complete-re, verilog-calc-1): Teach verilog-mode to properly indent after a DPI import/export statement that resides outside of a module. Reported by Kaushal Modi. (verilog-extended-complete-re): Update regexp to match both "DPI-C" and "DPI". Reported by Kaushal Modi.
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