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-rw-r--r--lisp/progmodes/verilog-mode.el769
1 files changed, 415 insertions, 354 deletions
diff --git a/lisp/progmodes/verilog-mode.el b/lisp/progmodes/verilog-mode.el
index e92647dbbac..a949a461c11 100644
--- a/lisp/progmodes/verilog-mode.el
+++ b/lisp/progmodes/verilog-mode.el
@@ -108,7 +108,6 @@
;; verilog-minimum-comment-distance 40
;; verilog-indent-begin-after-if t
;; verilog-auto-lineup 'declarations
-;; verilog-highlight-p1800-keywords nil
;; verilog-linter "my_lint_shell_command"
;; )
@@ -122,7 +121,7 @@
;;
;; This variable will always hold the version number of the mode
-(defconst verilog-mode-version "2017-08-07-c085e50-vpo-GNU"
+(defconst verilog-mode-version "2018-11-26-bb3814b-vpo-GNU"
"Version of this Verilog mode.")
(defconst verilog-mode-release-emacs t
"If non-nil, this version of Verilog mode was released with Emacs itself.")
@@ -238,7 +237,7 @@ STRING should be given if the last search was by `string-match' on STRING."
(unless (featurep 'xemacs)
(unless (fboundp 'region-active-p)
(defmacro region-active-p ()
- `(and transient-mark-mode mark-active))))
+ '(and transient-mark-mode mark-active))))
)
;; Provide a regular expression optimization routine, using regexp-opt
@@ -250,7 +249,7 @@ STRING should be given if the last search was by `string-match' on STRING."
(if (fboundp 'regexp-opt)
;; regexp-opt is defined, does it take 3 or 2 arguments?
(if (fboundp 'function-max-args)
- (let ((args (function-max-args `regexp-opt)))
+ (let ((args (function-max-args 'regexp-opt)))
(cond
((eq args 3) ; It takes 3
(condition-case nil ; Hide this defun from emacses
@@ -382,7 +381,7 @@ wherever possible, since it is slow."
((vectorp menu)
(let ((i 0) (out []))
(while (< i (length menu))
- (if (equal `:help (aref menu i))
+ (if (equal :help (aref menu i))
(setq i (+ 2 i))
(setq out (vconcat out (vector (aref menu i)))
i (1+ i))))
@@ -719,15 +718,13 @@ default avoids too many redundant comments in tight quarters."
(put 'verilog-minimum-comment-distance 'safe-local-variable 'integerp)
(defcustom verilog-highlight-p1800-keywords nil
- "Non-nil means highlight words newly reserved by IEEE-1800.
-These will appear in `verilog-font-lock-p1800-face' in order to gently
-suggest changing where these words are used as variables to something else.
-A nil value means highlight these words as appropriate for the SystemVerilog
-IEEE-1800 standard. Note that changing this will require restarting Emacs
-to see the effect as font color choices are cached by Emacs."
+ "Obsolete.
+Was non-nil means highlight SystemVerilog IEEE-1800 differently.
+All code is now highlighted as if SystemVerilog IEEE-1800."
:group 'verilog-mode-indent
:type 'boolean)
(put 'verilog-highlight-p1800-keywords 'safe-local-variable 'verilog-booleanp)
+(make-obsolete-variable 'verilog-highlight-p1800-keywords nil "27.1")
(defcustom verilog-highlight-grouping-keywords nil
"Non-nil means highlight grouping keywords more dramatically.
@@ -1070,6 +1067,18 @@ of each Verilog file that requires it, rather than being set globally."
:type 'boolean)
(put 'verilog-auto-sense-defines-constant 'safe-local-variable 'verilog-booleanp)
+(defcustom verilog-auto-simplify-expressions t
+ "Non-nil means AUTOs will simplify expressions when calculating bit ranges.
+When nil, do not simply ranges, which may simplify the output,
+but may cause problems when there are multiple instantiations
+outputting to the same wire. To maintain compatibility with
+other sites, this should be set at the bottom of each Verilog
+file that requires it, rather than being set globally."
+ :version "27.1"
+ :group 'verilog-mode-auto
+ :type 'boolean)
+(put 'verilog-auto-simplify-expressions 'safe-local-variable 'verilog-booleanp)
+
(defcustom verilog-auto-reset-blocking-in-non t
"Non-nil means AUTORESET will reset blocking statements.
When true, AUTORESET will reset in blocking statements those
@@ -1389,7 +1398,7 @@ See also `verilog-case-fold'."
("*Variables*" "^\\s-*\\(reg\\|wire\\|logic\\)\\s-+\\(\\|\\[[^]]+\\]\\s-+\\)\\([A-Za-z0-9_]+\\)" 3)
("*Classes*" "^\\s-*\\(?:\\(?:virtual\\|interface\\)\\s-+\\)?class\\s-+\\([A-Za-z_][A-Za-z0-9_]+\\)" 1)
("*Tasks*" "^\\s-*\\(?:\\(?:static\\|pure\\|virtual\\|local\\|protected\\)\\s-+\\)*task\\s-+\\(?:\\(?:static\\|automatic\\)\\s-+\\)?\\([A-Za-z_][A-Za-z0-9_:]+\\)" 1)
- ("*Functions*" "^\\s-*\\(?:\\(?:static\\|pure\\|virtual\\|local\\|protected\\)\\s-+\\)*function\\s-+\\(?:\\(?:static\\|automatic\\)\\s-+\\)?\\(?:\\w+\\s-+\\)?\\([A-Za-z_][A-Za-z0-9_:]+\\)" 1)
+ ("*Functions*" "^\\s-*\\(?:\\(?:static\\|pure\\|virtual\\|local\\|protected\\)\\s-+\\)*function\\s-+\\(?:\\(?:static\\|automatic\\)\\s-+\\)?\\(?:\\w+\\s-+\\)?\\(?:\\(?:un\\)signed\\s-+\\)?\\([A-Za-z_][A-Za-z0-9_:]+\\)" 1)
("*Interfaces*" "^\\s-*interface\\s-+\\([a-zA-Z_0-9]+\\)" 1)
("*Types*" "^\\s-*typedef\\s-+.*\\s-+\\([a-zA-Z_0-9]+\\)\\s-*;" 1))
"Imenu expression for Verilog mode. See `imenu-generic-expression'.")
@@ -1432,7 +1441,7 @@ If set will become buffer local.")
(define-key map [(meta delete)] 'kill-word))
(define-key map "\M-\C-b" 'electric-verilog-backward-sexp)
(define-key map "\M-\C-f" 'electric-verilog-forward-sexp)
- (define-key map "\M-\r" `electric-verilog-terminate-and-indent)
+ (define-key map "\M-\r" 'electric-verilog-terminate-and-indent)
(define-key map "\M-\t" (if (fboundp 'completion-at-point)
'completion-at-point 'verilog-complete-word))
(define-key map "\M-?" (if (fboundp 'completion-help-at-point)
@@ -1481,35 +1490,35 @@ If set will become buffer local.")
(setq verilog-tool 'verilog-linter)
(verilog-set-compile-command))
:style radio
- :selected (equal verilog-tool `verilog-linter)
+ :selected (equal verilog-tool 'verilog-linter)
:help "When invoking compilation, use lint checker"]
["Coverage"
(progn
(setq verilog-tool 'verilog-coverage)
(verilog-set-compile-command))
:style radio
- :selected (equal verilog-tool `verilog-coverage)
+ :selected (equal verilog-tool 'verilog-coverage)
:help "When invoking compilation, annotate for coverage"]
["Simulator"
(progn
(setq verilog-tool 'verilog-simulator)
(verilog-set-compile-command))
:style radio
- :selected (equal verilog-tool `verilog-simulator)
+ :selected (equal verilog-tool 'verilog-simulator)
:help "When invoking compilation, interpret Verilog source"]
["Compiler"
(progn
(setq verilog-tool 'verilog-compiler)
(verilog-set-compile-command))
:style radio
- :selected (equal verilog-tool `verilog-compiler)
+ :selected (equal verilog-tool 'verilog-compiler)
:help "When invoking compilation, compile Verilog source"]
["Preprocessor"
(progn
(setq verilog-tool 'verilog-preprocessor)
(verilog-set-compile-command))
:style radio
- :selected (equal verilog-tool `verilog-preprocessor)
+ :selected (equal verilog-tool 'verilog-preprocessor)
:help "When invoking compilation, preprocess Verilog source, see also `verilog-preprocess'"]
)
("Move"
@@ -1728,29 +1737,29 @@ If set will become buffer local.")
:enable-function (lambda () (not (verilog-in-comment-or-string-p))))
(verilog-define-abbrev verilog-mode-abbrev-table "class" "" 'verilog-sk-ovm-class)
(verilog-define-abbrev verilog-mode-abbrev-table "always" "" 'verilog-sk-always)
-(verilog-define-abbrev verilog-mode-abbrev-table "begin" nil `verilog-sk-begin)
-(verilog-define-abbrev verilog-mode-abbrev-table "case" "" `verilog-sk-case)
-(verilog-define-abbrev verilog-mode-abbrev-table "for" "" `verilog-sk-for)
-(verilog-define-abbrev verilog-mode-abbrev-table "generate" "" `verilog-sk-generate)
-(verilog-define-abbrev verilog-mode-abbrev-table "initial" "" `verilog-sk-initial)
-(verilog-define-abbrev verilog-mode-abbrev-table "fork" "" `verilog-sk-fork)
-(verilog-define-abbrev verilog-mode-abbrev-table "module" "" `verilog-sk-module)
-(verilog-define-abbrev verilog-mode-abbrev-table "primitive" "" `verilog-sk-primitive)
-(verilog-define-abbrev verilog-mode-abbrev-table "repeat" "" `verilog-sk-repeat)
-(verilog-define-abbrev verilog-mode-abbrev-table "specify" "" `verilog-sk-specify)
-(verilog-define-abbrev verilog-mode-abbrev-table "task" "" `verilog-sk-task)
-(verilog-define-abbrev verilog-mode-abbrev-table "while" "" `verilog-sk-while)
-(verilog-define-abbrev verilog-mode-abbrev-table "casex" "" `verilog-sk-casex)
-(verilog-define-abbrev verilog-mode-abbrev-table "casez" "" `verilog-sk-casez)
-(verilog-define-abbrev verilog-mode-abbrev-table "if" "" `verilog-sk-if)
-(verilog-define-abbrev verilog-mode-abbrev-table "else if" "" `verilog-sk-else-if)
-(verilog-define-abbrev verilog-mode-abbrev-table "assign" "" `verilog-sk-assign)
-(verilog-define-abbrev verilog-mode-abbrev-table "function" "" `verilog-sk-function)
-(verilog-define-abbrev verilog-mode-abbrev-table "input" "" `verilog-sk-input)
-(verilog-define-abbrev verilog-mode-abbrev-table "output" "" `verilog-sk-output)
-(verilog-define-abbrev verilog-mode-abbrev-table "inout" "" `verilog-sk-inout)
-(verilog-define-abbrev verilog-mode-abbrev-table "wire" "" `verilog-sk-wire)
-(verilog-define-abbrev verilog-mode-abbrev-table "reg" "" `verilog-sk-reg)
+(verilog-define-abbrev verilog-mode-abbrev-table "begin" nil 'verilog-sk-begin)
+(verilog-define-abbrev verilog-mode-abbrev-table "case" "" 'verilog-sk-case)
+(verilog-define-abbrev verilog-mode-abbrev-table "for" "" 'verilog-sk-for)
+(verilog-define-abbrev verilog-mode-abbrev-table "generate" "" 'verilog-sk-generate)
+(verilog-define-abbrev verilog-mode-abbrev-table "initial" "" 'verilog-sk-initial)
+(verilog-define-abbrev verilog-mode-abbrev-table "fork" "" 'verilog-sk-fork)
+(verilog-define-abbrev verilog-mode-abbrev-table "module" "" 'verilog-sk-module)
+(verilog-define-abbrev verilog-mode-abbrev-table "primitive" "" 'verilog-sk-primitive)
+(verilog-define-abbrev verilog-mode-abbrev-table "repeat" "" 'verilog-sk-repeat)
+(verilog-define-abbrev verilog-mode-abbrev-table "specify" "" 'verilog-sk-specify)
+(verilog-define-abbrev verilog-mode-abbrev-table "task" "" 'verilog-sk-task)
+(verilog-define-abbrev verilog-mode-abbrev-table "while" "" 'verilog-sk-while)
+(verilog-define-abbrev verilog-mode-abbrev-table "casex" "" 'verilog-sk-casex)
+(verilog-define-abbrev verilog-mode-abbrev-table "casez" "" 'verilog-sk-casez)
+(verilog-define-abbrev verilog-mode-abbrev-table "if" "" 'verilog-sk-if)
+(verilog-define-abbrev verilog-mode-abbrev-table "else if" "" 'verilog-sk-else-if)
+(verilog-define-abbrev verilog-mode-abbrev-table "assign" "" 'verilog-sk-assign)
+(verilog-define-abbrev verilog-mode-abbrev-table "function" "" 'verilog-sk-function)
+(verilog-define-abbrev verilog-mode-abbrev-table "input" "" 'verilog-sk-input)
+(verilog-define-abbrev verilog-mode-abbrev-table "output" "" 'verilog-sk-output)
+(verilog-define-abbrev verilog-mode-abbrev-table "inout" "" 'verilog-sk-inout)
+(verilog-define-abbrev verilog-mode-abbrev-table "wire" "" 'verilog-sk-wire)
+(verilog-define-abbrev verilog-mode-abbrev-table "reg" "" 'verilog-sk-reg)
;;
;; Macros
@@ -2402,7 +2411,7 @@ find the errors."
(defconst verilog-assignment-operator-re
(eval-when-compile
(verilog-regexp-opt
- `(
+ '(
;; blocking assignment_operator
"=" "+=" "-=" "*=" "/=" "%=" "&=" "|=" "^=" "<<=" ">>=" "<<<=" ">>>="
;; non blocking assignment operator
@@ -2478,7 +2487,7 @@ find the errors."
verilog-directive-re "\\)\\|\\("
(eval-when-compile
(verilog-regexp-words
- `( "begin"
+ '( "begin"
"else"
"end"
"endcase"
@@ -2531,7 +2540,7 @@ find the errors."
(eval-when-compile
(verilog-regexp-words
- `("end" ; closes begin
+ '("end" ; closes begin
"endcase" ; closes any of case, casex casez or randcase
"join" "join_any" "join_none" ; closes fork
"endclass"
@@ -2601,7 +2610,7 @@ find the errors."
(defconst verilog-beg-block-re
(eval-when-compile
(verilog-regexp-words
- `("begin"
+ '("begin"
"case" "casex" "casez" "randcase"
"clocking"
"generate"
@@ -2677,7 +2686,7 @@ find the errors."
(defconst verilog-nameable-item-re
(eval-when-compile
(verilog-regexp-words
- `("begin"
+ '("begin"
"fork"
"join" "join_any" "join_none"
"end"
@@ -2704,12 +2713,12 @@ find the errors."
(defconst verilog-declaration-opener
(eval-when-compile
(verilog-regexp-words
- `("module" "begin" "task" "function"))))
+ '("module" "begin" "task" "function"))))
(defconst verilog-declaration-prefix-re
(eval-when-compile
(verilog-regexp-words
- `(
+ '(
;; port direction
"inout" "input" "output" "ref"
;; changeableness
@@ -2718,11 +2727,13 @@ find the errors."
"localparam" "parameter" "var"
;; type creation
"typedef"
+ ;; randomness
+ "rand"
))))
(defconst verilog-declaration-core-re
(eval-when-compile
(verilog-regexp-words
- `(
+ '(
;; port direction (by themselves)
"inout" "input" "output"
;; integer_atom_type
@@ -2764,25 +2775,25 @@ find the errors."
(defconst verilog-declaration-re-1-no-macro (concat "^" verilog-declaration-re-2-no-macro))
(defconst verilog-defun-re
- (eval-when-compile (verilog-regexp-words `("macromodule" "module" "class" "program" "interface" "package" "primitive" "config"))))
+ (eval-when-compile (verilog-regexp-words '("macromodule" "module" "class" "program" "interface" "package" "primitive" "config"))))
(defconst verilog-end-defun-re
- (eval-when-compile (verilog-regexp-words `("endmodule" "endclass" "endprogram" "endinterface" "endpackage" "endprimitive" "endconfig"))))
+ (eval-when-compile (verilog-regexp-words '("endmodule" "endclass" "endprogram" "endinterface" "endpackage" "endprimitive" "endconfig"))))
(defconst verilog-zero-indent-re
(concat verilog-defun-re "\\|" verilog-end-defun-re))
(defconst verilog-inst-comment-re
- (eval-when-compile (verilog-regexp-words `("Outputs" "Inouts" "Inputs" "Interfaces" "Interfaced"))))
+ (eval-when-compile (verilog-regexp-words '("Outputs" "Inouts" "Inputs" "Interfaces" "Interfaced"))))
(defconst verilog-behavioral-block-beg-re
- (eval-when-compile (verilog-regexp-words `("initial" "final" "always" "always_comb" "always_latch" "always_ff"
- "function" "task"))))
+ (eval-when-compile (verilog-regexp-words '("initial" "final" "always" "always_comb" "always_latch" "always_ff"
+ "function" "task"))))
(defconst verilog-coverpoint-re "\\w+\\s*:\\s*\\(coverpoint\\|cross\\constraint\\)" )
(defconst verilog-in-constraint-re ; keywords legal in constraint blocks starting a statement/block
- (eval-when-compile (verilog-regexp-words `("if" "else" "solve" "foreach"))))
+ (eval-when-compile (verilog-regexp-words '("if" "else" "solve" "foreach"))))
(defconst verilog-indent-re
(eval-when-compile
(verilog-regexp-words
- `(
+ '(
"{"
"always" "always_latch" "always_ff" "always_comb"
"begin" "end"
@@ -2866,28 +2877,28 @@ find the errors."
(defconst verilog-defun-level-not-generate-re
(eval-when-compile
(verilog-regexp-words
- `( "module" "macromodule" "primitive" "class" "program"
- "interface" "package" "config"))))
+ '( "module" "macromodule" "primitive" "class" "program"
+ "interface" "package" "config"))))
(defconst verilog-defun-level-re
(eval-when-compile
(verilog-regexp-words
(append
- `( "module" "macromodule" "primitive" "class" "program"
- "interface" "package" "config")
- `( "initial" "final" "always" "always_comb" "always_ff"
- "always_latch" "endtask" "endfunction" )))))
+ '( "module" "macromodule" "primitive" "class" "program"
+ "interface" "package" "config")
+ '( "initial" "final" "always" "always_comb" "always_ff"
+ "always_latch" "endtask" "endfunction" )))))
(defconst verilog-defun-level-generate-only-re
(eval-when-compile
(verilog-regexp-words
- `( "initial" "final" "always" "always_comb" "always_ff"
- "always_latch" "endtask" "endfunction" ))))
+ '( "initial" "final" "always" "always_comb" "always_ff"
+ "always_latch" "endtask" "endfunction" ))))
(defconst verilog-cpp-level-re
(eval-when-compile
(verilog-regexp-words
- `(
+ '(
"endmodule" "endprimitive" "endinterface" "endpackage" "endprogram" "endclass"
))))
@@ -2908,7 +2919,7 @@ find the errors."
(defconst verilog-basic-complete-re
(eval-when-compile
(verilog-regexp-words
- `(
+ '(
"always" "assign" "always_latch" "always_ff" "always_comb" "constraint"
"import" "initial" "final" "module" "macromodule" "repeat" "randcase" "while"
"if" "for" "forever" "foreach" "else" "parameter" "do" "localparam" "assert"
@@ -2937,7 +2948,7 @@ find the errors."
;; single words
"\\(?:"
(verilog-regexp-words
- `("`__FILE__"
+ '("`__FILE__"
"`__LINE__"
"`celldefine"
"`else"
@@ -3096,7 +3107,7 @@ See also `verilog-font-lock-extra-types'.")
(defvar verilog-font-lock-p1800-face
'verilog-font-lock-p1800-face
- "Font to use for p1800 keywords.")
+ "Obsolete font to use for p1800 keywords.")
(defface verilog-font-lock-p1800-face
'((((class color)
(background light))
@@ -3107,6 +3118,7 @@ See also `verilog-font-lock-extra-types'.")
(t (:italic t)))
"Font lock mode face used to highlight P1800 keywords."
:group 'font-lock-highlighting-faces)
+(make-obsolete-variable 'verilog-font-lock-p1800-face nil "27.1")
(defvar verilog-font-lock-ams-face
'verilog-font-lock-ams-face
@@ -3137,133 +3149,110 @@ See also `verilog-font-lock-extra-types'.")
:group 'font-lock-highlighting-faces)
(let* ((verilog-type-font-keywords
- (eval-when-compile
- (verilog-regexp-opt
- '(
- "and" "bit" "buf" "bufif0" "bufif1" "cmos" "defparam"
- "event" "genvar" "inout" "input" "integer" "localparam"
- "logic" "mailbox" "nand" "nmos" "nor" "not" "notif0" "notif1" "or"
- "output" "parameter" "pmos" "pull0" "pull1" "pulldown" "pullup"
- "rcmos" "real" "realtime" "reg" "rnmos" "rpmos" "rtran"
- "rtranif0" "rtranif1" "semaphore" "signed" "struct" "supply"
- "supply0" "supply1" "time" "tran" "tranif0" "tranif1"
- "tri" "tri0" "tri1" "triand" "trior" "trireg" "typedef"
- "uwire" "vectored" "wand" "wire" "wor" "xnor" "xor"
- ) nil )))
+ (eval-when-compile
+ (verilog-regexp-opt
+ '("and" "buf" "bufif0" "bufif1" "cmos" "defparam" "event"
+ "genvar" "highz0" "highz1" "inout" "input" "integer"
+ "localparam" "mailbox" "nand" "nmos" "nor" "not" "notif0"
+ "notif1" "or" "output" "parameter" "pmos" "pull0" "pull1"
+ "pulldown" "pullup" "rcmos" "real" "realtime" "reg" "rnmos"
+ "rpmos" "rtran" "rtranif0" "rtranif1" "semaphore" "signed"
+ "specparam" "strong0" "strong1" "supply" "supply0" "supply1"
+ "time" "tran" "tranif0" "tranif1" "tri" "tri0" "tri1" "triand"
+ "trior" "trireg" "unsigned" "uwire" "vectored" "wand" "weak0"
+ "weak1" "wire" "wor" "xnor" "xor"
+ ;; 1800-2005
+ "bit" "byte" "chandle" "const" "enum" "int" "logic" "longint"
+ "packed" "ref" "shortint" "shortreal" "static" "string"
+ "struct" "type" "typedef" "union" "var"
+ ;; 1800-2009
+ ;; 1800-2012
+ "interconnect" "nettype" ) nil)))
(verilog-pragma-keywords
- (eval-when-compile
- (verilog-regexp-opt
- '("surefire" "auto" "synopsys" "rtl_synthesis" "verilint" "leda" "0in"
- ) nil )))
-
- (verilog-1800-2005-keywords
- (eval-when-compile
- (verilog-regexp-opt
- '("alias" "assert" "assume" "automatic" "before" "bind"
- "bins" "binsof" "break" "byte" "cell" "chandle" "class"
- "clocking" "config" "const" "constraint" "context" "continue"
- "cover" "covergroup" "coverpoint" "cross" "deassign" "design"
- "dist" "do" "edge" "endclass" "endclocking" "endconfig"
- "endgroup" "endprogram" "endproperty" "endsequence" "enum"
- "expect" "export" "extends" "extern" "first_match" "foreach"
- "forkjoin" "genvar" "highz0" "highz1" "ifnone" "ignore_bins"
- "illegal_bins" "import" "incdir" "include" "inside" "instance"
- "int" "intersect" "large" "liblist" "library" "local" "longint"
- "matches" "medium" "modport" "new" "noshowcancelled" "null"
- "packed" "program" "property" "protected" "pull0" "pull1"
- "pulsestyle_onevent" "pulsestyle_ondetect" "pure" "rand" "randc"
- "randcase" "randsequence" "ref" "release" "return" "scalared"
- "sequence" "shortint" "shortreal" "showcancelled" "small" "solve"
- "specparam" "static" "string" "strong0" "strong1" "struct"
- "super" "tagged" "this" "throughout" "timeprecision" "timeunit"
- "type" "union" "unsigned" "use" "var" "virtual" "void"
- "wait_order" "weak0" "weak1" "wildcard" "with" "within"
- ) nil )))
-
- (verilog-1800-2009-keywords
- (eval-when-compile
- (verilog-regexp-opt
- '("accept_on" "checker" "endchecker" "eventually" "global"
- "implies" "let" "nexttime" "reject_on" "restrict" "s_always"
- "s_eventually" "s_nexttime" "s_until" "s_until_with" "strong"
- "sync_accept_on" "sync_reject_on" "unique0" "until"
- "until_with" "untyped" "weak" ) nil )))
-
- (verilog-1800-2012-keywords
- (eval-when-compile
- (verilog-regexp-opt
- '("implements" "interconnect" "nettype" "soft" ) nil )))
+ (eval-when-compile
+ (verilog-regexp-opt
+ '("surefire" "0in" "auto" "leda" "rtl_synthesis" "synopsys"
+ "verilint" ) nil)))
(verilog-ams-keywords
- (eval-when-compile
- (verilog-regexp-opt
- '("above" "abs" "absdelay" "acos" "acosh" "ac_stim"
- "aliasparam" "analog" "analysis" "asin" "asinh" "atan" "atan2" "atanh"
- "branch" "ceil" "connectmodule" "connectrules" "cos" "cosh" "ddt"
- "ddx" "discipline" "driver_update" "enddiscipline" "endconnectrules"
- "endnature" "endparamset" "exclude" "exp" "final_step" "flicker_noise"
- "floor" "flow" "from" "ground" "hypot" "idt" "idtmod" "inf"
- "initial_step" "laplace_nd" "laplace_np" "laplace_zd" "laplace_zp"
- "last_crossing" "limexp" "ln" "log" "max" "min" "nature"
- "net_resolution" "noise_table" "paramset" "potential" "pow" "sin"
- "sinh" "slew" "sqrt" "tan" "tanh" "timer" "transition" "white_noise"
- "wreal" "zi_nd" "zi_np" "zi_zd" ) nil )))
-
- (verilog-font-keywords
- (eval-when-compile
- (verilog-regexp-opt
- '(
- "assign" "case" "casex" "casez" "randcase" "deassign"
- "default" "disable" "else" "endcase" "endfunction"
- "endgenerate" "endinterface" "endmodule" "endprimitive"
- "endspecify" "endtable" "endtask" "final" "for" "force" "return" "break"
- "continue" "forever" "fork" "function" "generate" "if" "iff" "initial"
- "interface" "join" "join_any" "join_none" "macromodule" "module" "negedge"
- "package" "endpackage" "always" "always_comb" "always_ff"
- "always_latch" "posedge" "primitive" "priority" "release"
- "repeat" "specify" "table" "task" "unique" "wait" "while"
- "class" "program" "endclass" "endprogram"
- ) nil )))
+ (eval-when-compile
+ (verilog-regexp-opt
+ '("above" "abs" "absdelay" "abstol" "ac_stim" "access" "acos"
+ "acosh" "aliasparam" "analog" "analysis" "asin" "asinh" "atan"
+ "atan2" "atanh" "branch" "ceil" "connect" "connectmodule"
+ "connectrules" "continuous" "cos" "cosh" "ddt" "ddt_nature"
+ "ddx" "discipline" "discrete" "domain" "driver_update"
+ "endconnectrules" "enddiscipline" "endnature" "endparamset"
+ "exclude" "exp" "final_step" "flicker_noise" "floor" "flow"
+ "from" "ground" "hypot" "idt" "idt_nature" "idtmod" "inf"
+ "initial_step" "laplace_nd" "laplace_np" "laplace_zd"
+ "laplace_zp" "last_crossing" "limexp" "ln" "log" "max"
+ "merged" "min" "nature" "net_resolution" "noise_table"
+ "paramset" "potential" "pow" "resolveto" "sin" "sinh" "slew"
+ "split" "sqrt" "tan" "tanh" "timer" "transition" "units"
+ "white_noise" "wreal" "zi_nd" "zi_np" "zi_zd" "zi_zp"
+ ;; Excluded AMS keywords: "assert" "cross" "string"
+ ) nil)))
+
+ (verilog-font-general-keywords
+ (eval-when-compile
+ (verilog-regexp-opt
+ '("always" "assign" "automatic" "case" "casex" "casez" "cell"
+ "config" "deassign" "default" "design" "disable" "edge" "else"
+ "endcase" "endconfig" "endfunction" "endgenerate" "endmodule"
+ "endprimitive" "endspecify" "endtable" "endtask" "for" "force"
+ "forever" "fork" "function" "generate" "if" "ifnone" "incdir"
+ "include" "initial" "instance" "join" "large" "liblist"
+ "library" "macromodule" "medium" "module" "negedge"
+ "noshowcancelled" "posedge" "primitive" "pulsestyle_ondetect"
+ "pulsestyle_onevent" "release" "repeat" "scalared"
+ "showcancelled" "small" "specify" "strength" "table" "task"
+ "use" "wait" "while"
+ ;; 1800-2005
+ "alias" "always_comb" "always_ff" "always_latch" "assert"
+ "assume" "before" "bind" "bins" "binsof" "break" "class"
+ "clocking" "constraint" "context" "continue" "cover"
+ "covergroup" "coverpoint" "cross" "dist" "do" "endclass"
+ "endclocking" "endgroup" "endinterface" "endpackage"
+ "endprogram" "endproperty" "endsequence" "expect" "export"
+ "extends" "extern" "final" "first_match" "foreach" "forkjoin"
+ "iff" "ignore_bins" "illegal_bins" "import" "inside"
+ "interface" "intersect" "join_any" "join_none" "local"
+ "matches" "modport" "new" "null" "package" "priority"
+ "program" "property" "protected" "pure" "rand" "randc"
+ "randcase" "randsequence" "return" "sequence" "solve" "super"
+ "tagged" "this" "throughout" "timeprecision" "timeunit"
+ "unique" "virtual" "void" "wait_order" "wildcard" "with"
+ "within"
+ ;; 1800-2009
+ "accept_on" "checker" "endchecker" "eventually" "global"
+ "implies" "let" "nexttime" "reject_on" "restrict" "s_always"
+ "s_eventually" "s_nexttime" "s_until" "s_until_with" "strong"
+ "sync_accept_on" "sync_reject_on" "unique0" "until"
+ "until_with" "untyped" "weak"
+ ;; 1800-2012
+ "implements" "soft" ) nil)))
(verilog-font-grouping-keywords
- (eval-when-compile
- (verilog-regexp-opt
- '( "begin" "end" ) nil ))))
+ (eval-when-compile
+ (verilog-regexp-opt
+ '( "begin" "end" ) nil))))
(setq verilog-font-lock-keywords
(list
;; Fontify all builtin keywords
- (concat "\\<\\(" verilog-font-keywords "\\|"
+ (concat "\\<\\(" verilog-font-general-keywords "\\|"
;; And user/system tasks and functions
"\\$[a-zA-Z][a-zA-Z0-9_\\$]*"
"\\)\\>")
;; Fontify all types
- (if verilog-highlight-grouping-keywords
- (cons (concat "\\<\\(" verilog-font-grouping-keywords "\\)\\>")
- 'verilog-font-lock-grouping-keywords-face)
- (cons (concat "\\<\\(" verilog-font-grouping-keywords "\\)\\>")
+ (cons (concat "\\<\\(" verilog-font-grouping-keywords "\\)\\>")
+ (if verilog-highlight-grouping-keywords
+ 'verilog-font-lock-grouping-keywords-face
'font-lock-type-face))
(cons (concat "\\<\\(" verilog-type-font-keywords "\\)\\>")
'font-lock-type-face)
- ;; Fontify IEEE-1800-2005 keywords appropriately
- (if verilog-highlight-p1800-keywords
- (cons (concat "\\<\\(" verilog-1800-2005-keywords "\\)\\>")
- 'verilog-font-lock-p1800-face)
- (cons (concat "\\<\\(" verilog-1800-2005-keywords "\\)\\>")
- 'font-lock-type-face))
- ;; Fontify IEEE-1800-2009 keywords appropriately
- (if verilog-highlight-p1800-keywords
- (cons (concat "\\<\\(" verilog-1800-2009-keywords "\\)\\>")
- 'verilog-font-lock-p1800-face)
- (cons (concat "\\<\\(" verilog-1800-2009-keywords "\\)\\>")
- 'font-lock-type-face))
- ;; Fontify IEEE-1800-2012 keywords appropriately
- (if verilog-highlight-p1800-keywords
- (cons (concat "\\<\\(" verilog-1800-2012-keywords "\\)\\>")
- 'verilog-font-lock-p1800-face)
- (cons (concat "\\<\\(" verilog-1800-2012-keywords "\\)\\>")
- 'font-lock-type-face))
;; Fontify Verilog-AMS keywords
(cons (concat "\\<\\(" verilog-ams-keywords "\\)\\>")
'verilog-font-lock-ams-face)))
@@ -3492,7 +3481,7 @@ either is ok to parse as a non-comment, or `verilog-insert' was used."
(remove-text-properties (point-min) (point-max) '(face nil))
(while (not (eobp))
(cond ((get-text-property (point) 'v-cmts)
- (put-text-property (point) (1+ (point)) `face 'underline)
+ (put-text-property (point) (1+ (point)) 'face 'underline)
;;(if dbg (setq dbg (concat dbg (format " v-cmts at %S\n" (point)))))
(forward-char 1))
(t
@@ -3960,13 +3949,15 @@ Key bindings specific to `verilog-mode-map' are:
(setq hs-special-modes-alist
(cons '(verilog-mode "\\<begin\\>" "\\<end\\>" nil
verilog-forward-sexp-function)
- hs-special-modes-alist))))
+ hs-special-modes-alist))))
(add-hook 'completion-at-point-functions
#'verilog-completion-at-point nil 'local)
;; Stuff for autos
- (add-hook 'write-contents-hooks 'verilog-auto-save-check nil 'local)
+ (add-hook (if (boundp 'write-contents-hooks) 'write-contents-hooks
+ 'write-contents-functions) ; Emacs >= 22.1
+ 'verilog-auto-save-check nil 'local)
;; verilog-mode-hook call added by define-derived-mode
)
@@ -4162,6 +4153,7 @@ With optional ARG, remove existing end of line comments."
To call this from the command line, see \\[verilog-batch-indent]."
(interactive)
(verilog-mode)
+ (verilog-auto-reeval-locals)
(indent-region (point-min) (point-max) nil))
(defun verilog-insert-block ()
@@ -4983,21 +4975,21 @@ primitive or interface named NAME."
(match-end 11) ; of verilog-end-block-ordered-re
;;(goto-char there)
(let ((nest 0)
- (reg "\\<\\(class\\)\\|\\(endclass\\)\\|\\(package\\|primitive\\|\\(macro\\)?module\\)\\>")
+ (reg "\\<\\(\\(class\\)\\|\\(endclass\\)\\|\\(package\\|primitive\\|\\(macro\\)?module\\)\\)\\>")
string)
(save-excursion
(catch 'skip
(while (verilog-re-search-backward reg nil 'move)
(cond
- ((match-end 3) ; endclass
+ ((match-end 4) ; endclass
(ding 't)
(setq string "unmatched endclass")
(throw 'skip 1))
- ((match-end 2) ; endclass
+ ((match-end 3) ; endclass
(setq nest (1+ nest)))
- ((match-end 1) ; class
+ ((match-end 2) ; class
(setq nest (1- nest))
(if (< nest 0)
(progn
@@ -5235,11 +5227,11 @@ Useful for creating tri's and other expanded fields."
compile-command))
(lint-word1 (verilog-string-replace-matches "\\s .*$" "" nil nil
verilog-linter)))
- (cond ((equal compile-word1 "surelint") `surelint)
- ((equal compile-word1 "verilint") `verilint)
- ((equal lint-word1 "surelint") `surelint)
- ((equal lint-word1 "verilint") `verilint)
- (t `surelint)))) ; back compatibility
+ (cond ((equal compile-word1 "surelint") 'surelint)
+ ((equal compile-word1 "verilint") 'verilint)
+ ((equal lint-word1 "surelint") 'surelint)
+ ((equal lint-word1 "verilint") 'verilint)
+ (t 'surelint)))) ; back compatibility
(defun verilog-lint-off ()
"Convert a Verilog linter warning line into a disable statement.
@@ -5253,9 +5245,9 @@ variables is used to determine which product is being used.
See \\[verilog-surelint-off] and \\[verilog-verilint-off]."
(interactive)
(let ((linter (verilog-linter-name)))
- (cond ((equal linter `surelint)
+ (cond ((equal linter 'surelint)
(verilog-surelint-off))
- ((equal linter `verilint)
+ ((equal linter 'verilint)
(verilog-verilint-off))
(t (error "Linter name not set")))))
@@ -5359,7 +5351,7 @@ FILENAME to find directory to run in, or defaults to `buffer-file-name'."
(interactive
(list
(let ((default (verilog-expand-command verilog-preprocessor)))
- (set (make-local-variable `verilog-preprocessor)
+ (set (make-local-variable 'verilog-preprocessor)
(read-from-minibuffer "Run Preprocessor (like this): "
default nil nil
'verilog-preprocess-history default)))))
@@ -5405,6 +5397,9 @@ This lets programs calling batch mode to easily extract error messages."
(error "%%Error: %s%s" (error-message-string err)
(if (featurep 'xemacs) "\n" "")))))) ; XEmacs forgets to add a newline
+;; Eliminate compile warning
+(defvar verilog-batch-orig-buffer-string)
+
(defun verilog-batch-execute-func (funref &optional no-save)
"Internal processing of a batch command.
Runs FUNREF on all command arguments.
@@ -5426,26 +5421,31 @@ Save the result unless optional NO-SAVE is t."
;; Remember buffer list, so don't later pickup any verilog-getopt files
(let ((orig-buffer-list (buffer-list)))
(mapc (lambda (buf)
- (when (buffer-file-name buf)
- (with-current-buffer buf
- (verilog-mode)
- (verilog-auto-reeval-locals)
- (verilog-getopt-flags))))
- orig-buffer-list)
+ (when (buffer-file-name buf)
+ (with-current-buffer buf
+ (set (make-local-variable 'verilog-batch-orig-buffer-string)
+ (buffer-string))
+ (put 'verilog-batch-orig-buffer-string 'permanent-local t)
+ (verilog-mode)
+ (verilog-auto-reeval-locals)
+ (verilog-getopt-flags))))
+ orig-buffer-list)
;; Process the files
- (mapcar (lambda (buf)
- (when (buffer-file-name buf)
- (save-excursion
- (if (not (file-exists-p (buffer-file-name buf)))
- (error
- "File not found: %s" (buffer-file-name buf)))
- (message "Processing %s" (buffer-file-name buf))
- (set-buffer buf)
- (funcall funref)
- (when (and (not no-save)
- (buffer-modified-p)) ; Avoid "no changes to be saved"
- (save-buffer)))))
- orig-buffer-list))))
+ (mapc (lambda (buf)
+ (when (buffer-file-name buf)
+ (save-excursion
+ (if (not (file-exists-p (buffer-file-name buf)))
+ (error
+ "File not found: %s" (buffer-file-name buf)))
+ (message "Processing %s" (buffer-file-name buf))
+ (set-buffer buf)
+ (funcall funref)
+ (verilog-star-cleanup)
+ (when (and (not no-save)
+ (buffer-modified-p)
+ (not (equal verilog-batch-orig-buffer-string (buffer-string))))
+ (save-buffer)))))
+ orig-buffer-list))))
(defun verilog-batch-auto ()
"For use with --batch, perform automatic expansions as a stand-alone tool.
@@ -5455,7 +5455,7 @@ For proper results, multiple filenames need to be passed on the command
line in bottom-up order."
(unless noninteractive
(error "Use verilog-batch-auto only with --batch")) ; Otherwise we'd mess up buffer modes
- (verilog-batch-execute-func `verilog-auto))
+ (verilog-batch-execute-func 'verilog-auto))
(defun verilog-batch-delete-auto ()
"For use with --batch, perform automatic deletion as a stand-alone tool.
@@ -5463,7 +5463,7 @@ This sets up the appropriate Verilog mode environment, deletes automatics
with \\[verilog-delete-auto] on all command-line files, and saves the buffers."
(unless noninteractive
(error "Use verilog-batch-delete-auto only with --batch")) ; Otherwise we'd mess up buffer modes
- (verilog-batch-execute-func `verilog-delete-auto))
+ (verilog-batch-execute-func 'verilog-delete-auto))
(defun verilog-batch-delete-trailing-whitespace ()
"For use with --batch, perform whitespace deletion as a stand-alone tool.
@@ -5472,7 +5472,7 @@ whitespace with \\[verilog-delete-trailing-whitespace] on all
command-line files, and saves the buffers."
(unless noninteractive
(error "Use verilog-batch-delete-trailing-whitespace only with --batch")) ; Otherwise we'd mess up buffer modes
- (verilog-batch-execute-func `verilog-delete-trailing-whitespace))
+ (verilog-batch-execute-func 'verilog-delete-trailing-whitespace))
(defun verilog-batch-diff-auto ()
"For use with --batch, perform automatic differences as a stand-alone tool.
@@ -5482,7 +5482,7 @@ if any differences are observed. This is appropriate for adding to regressions
to insure automatics are always properly maintained."
(unless noninteractive
(error "Use verilog-batch-diff-auto only with --batch")) ; Otherwise we'd mess up buffer modes
- (verilog-batch-execute-func `verilog-diff-auto t))
+ (verilog-batch-execute-func 'verilog-diff-auto t))
(defun verilog-batch-inject-auto ()
"For use with --batch, perform automatic injection as a stand-alone tool.
@@ -5492,7 +5492,7 @@ For proper results, multiple filenames need to be passed on the command
line in bottom-up order."
(unless noninteractive
(error "Use verilog-batch-inject-auto only with --batch")) ; Otherwise we'd mess up buffer modes
- (verilog-batch-execute-func `verilog-inject-auto))
+ (verilog-batch-execute-func 'verilog-inject-auto))
(defun verilog-batch-indent ()
"For use with --batch, reindent an entire file as a stand-alone tool.
@@ -5500,7 +5500,7 @@ This sets up the appropriate Verilog mode environment, calls
\\[verilog-indent-buffer] on all command-line files, and saves the buffers."
(unless noninteractive
(error "Use verilog-batch-indent only with --batch")) ; Otherwise we'd mess up buffer modes
- (verilog-batch-execute-func `verilog-indent-buffer))
+ (verilog-batch-execute-func 'verilog-indent-buffer))
;;; Indentation:
;;
@@ -6406,7 +6406,7 @@ Return >0 for nested struct."
(equal (char-before) ?\;)
(equal (char-before) ?\}))
;; skip what looks like bus repetition operator {#{
- (not (string-match "^{\\s-*[0-9]+\\s-*{" (buffer-substring p (point)))))))))
+ (not (string-match "^{\\s-*[0-9a-zA-Z_]+\\s-*{" (buffer-substring p (point)))))))))
(progn
(let ( (pt (point)) (pass 0))
(verilog-backward-ws&directives)
@@ -6424,9 +6424,11 @@ Return >0 for nested struct."
;; check next word token
(if (looking-at "\\<\\w+\\>\\|\\s-*(\\s-*\\S-+")
(progn (verilog-beg-of-statement)
- (if (looking-at (concat "\\<\\(constraint\\|"
+ (if (and
+ (not (string-match verilog-named-block-re (buffer-substring pt (point)))) ;; Abort if 'begin' keyword is found
+ (looking-at (concat "\\<\\(constraint\\|"
"\\(?:\\w+\\s-*:\\s-*\\)?\\(coverpoint\\|cross\\)"
- "\\|with\\)\\>\\|" verilog-in-constraint-re))
+ "\\|with\\)\\>\\|" verilog-in-constraint-re)))
(setq pass 1)))))
(if (eq pass 0)
(progn (goto-char pt) nil) 1)))
@@ -7337,7 +7339,7 @@ will be completed at runtime and should not be added to this list.")
("xor" "output"))
"Map of direction for each positional argument to each gate primitive.")
-(defvar verilog-gate-keywords (mapcar `car verilog-gate-ios)
+(defvar verilog-gate-keywords (mapcar #'car verilog-gate-ios)
"Keywords for gate primitives.")
(defun verilog-string-diff (str1 str2)
@@ -8170,7 +8172,7 @@ Duplicate signals are also removed. For example A[2] and A[1] become A[2:1]."
sv-modport
bus)
;; Shove signals so duplicated signals will be adjacent
- (setq in-list (sort in-list `verilog-signals-sort-compare))
+ (setq in-list (sort in-list #'verilog-signals-sort-compare))
(while in-list
(setq sig (car in-list))
;; No current signal; form from existing details
@@ -8191,11 +8193,11 @@ Duplicate signals are also removed. For example A[2] and A[1] become A[2:1]."
(setq bus (verilog-sig-bits sig))
(setq bus (and bus (verilog-simplify-range-expression bus)))
(cond ((and bus
- (or (and (string-match "\\[\\([0-9]+\\):\\([0-9]+\\)\\]" bus)
+ (or (and (string-match "^\\[\\([0-9]+\\):\\([0-9]+\\)\\]$" bus)
(setq highbit (string-to-number (match-string 1 bus))
lowbit (string-to-number
(match-string 2 bus))))
- (and (string-match "\\[\\([0-9]+\\)\\]" bus)
+ (and (string-match "^\\[\\([0-9]+\\)\\]$" bus)
(setq highbit (string-to-number (match-string 1 bus))
lowbit highbit))))
;; Combine bits in bus
@@ -8429,7 +8431,7 @@ Optional NUM-PARAM and MAX-PARAM check for a specific number of parameters."
;; /*AUTOPUNT("parameter", "parameter")*/
(backward-sexp 1)
(while (looking-at "(?\\s *\"\\([^\"]*\\)\"\\s *,?")
- (setq olist (cons (match-string 1) olist))
+ (setq olist (cons (match-string-no-properties 1) olist))
(goto-char (match-end 0))))
(or (eq nil num-param)
(<= num-param (length olist))
@@ -8461,12 +8463,12 @@ Return an array of [outputs inouts inputs wire reg assign const]."
(cond
((looking-at "//")
(when (looking-at "[^\n]*\\(auto\\|synopsys\\)\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
- (setq enum (match-string 2)))
+ (setq enum (match-string-no-properties 2)))
(search-forward "\n"))
((looking-at "/\\*")
(forward-char 2)
(when (looking-at "[^\n]*\\(auto\\|synopsys\\)\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
- (setq enum (match-string 2)))
+ (setq enum (match-string-no-properties 2)))
(or (search-forward "*/")
(error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
((looking-at "(\\*")
@@ -8518,7 +8520,8 @@ Return an array of [outputs inouts inputs wire reg assign const]."
(cond (newsig ; Memory, not just width. Patch last signal added's memory (nth 3)
(setcar (cdr (cdr (cdr newsig)))
(if (verilog-sig-memory newsig)
- (concat (verilog-sig-memory newsig) (match-string 1))
+ (concat (verilog-sig-memory newsig)
+ (match-string-no-properties 1))
(match-string-no-properties 1))))
(vec ; Multidimensional
(setq multidim (cons vec multidim))
@@ -8532,14 +8535,14 @@ Return an array of [outputs inouts inputs wire reg assign const]."
(goto-char (match-end 0))
(setq last-keywd keywd
keywd (match-string-no-properties 1))
- (when (string-match "^\\\\" (match-string 1))
+ (when (string-match "^\\\\" (match-string-no-properties 1))
(setq keywd (concat keywd " "))) ; Escaped ID needs space at end
;; Add any :: package names to same identifier
;; '*' here is for "import x::*"
(while (looking-at "\\s-*::\\s-*\\(\\*\\|[a-zA-Z0-9`_$]+\\|\\\\[^ \t\n\f]+\\)")
(goto-char (match-end 0))
- (setq keywd (concat keywd "::" (match-string 1)))
- (when (string-match "^\\\\" (match-string 1))
+ (setq keywd (concat keywd "::" (match-string-no-properties 1)))
+ (when (string-match "^\\\\" (match-string-no-properties 1))
(setq keywd (concat keywd " ")))) ; Escaped ID needs space at end
(cond ((equal keywd "input")
(setq vec nil enum nil rvalue nil newsig nil signed nil
@@ -8624,10 +8627,12 @@ Return an array of [outputs inouts inputs wire reg assign const]."
((and v2kargs-ok
(eq paren 1)
(not rvalue)
- (looking-at "\\s-*\\(\\.\\(\\s-*[a-zA-Z`_$][a-zA-Z0-9`_$]*\\)\\|\\)\\s-*[a-zA-Z`_$][a-zA-Z0-9`_$]*"))
+ (or (looking-at "\\s-*#")
+ (looking-at "\\s-*\\(\\.\\(\\s-*[a-zA-Z`_$][a-zA-Z0-9`_$]*\\)\\|\\)\\s-*[a-zA-Z`_$][a-zA-Z0-9`_$]*")))
(when (match-end 2) (goto-char (match-end 2)))
(setq vec nil enum nil rvalue nil signed nil
- typedefed keywd multidim nil ptype nil modport (match-string 2)
+ typedefed keywd multidim nil ptype nil
+ modport (match-string-no-properties 2)
newsig nil sig-paren paren
expect-signal 'sigs-intf io t ))
;; Ignore dotted LHS assignments: "assign foo.bar = z;"
@@ -8676,7 +8681,8 @@ Return an array of [outputs inouts inputs wire reg assign const]."
((and expect-signal
(not rvalue)
(eq functask 0)
- (not (member keywd verilog-keywords)))
+ (not (member keywd verilog-keywords))
+ (or (not io) (eq paren sig-paren)))
;; Add new signal to expect-signal's variable
;;(if dbg (setq dbg (concat dbg (format "Pt %s New sig %s'\n" (point) keywd))))
(setq newsig (verilog-sig-new keywd vec nil nil enum signed typedefed multidim modport))
@@ -8741,7 +8747,7 @@ Return an array of [outputs inouts inputs wire reg assign const]."
(setq port (verilog-symbol-detick-denumber port))
(setq sig (if dotname port (verilog-symbol-detick-denumber sig)))
(if vec (setq vec (verilog-symbol-detick-denumber vec)))
- (if multidim (setq multidim (mapcar `verilog-symbol-detick-denumber multidim)))
+ (if multidim (setq multidim (mapcar #'verilog-symbol-detick-denumber multidim)))
(if mem (setq mem (verilog-symbol-detick-denumber mem)))
(unless (or (not sig)
(equal sig "")) ; Ignore .foo(1'b1) assignments
@@ -8849,8 +8855,9 @@ Return an array of [outputs inouts inputs wire reg assign const]."
;;(message "vrsde-s: `%s'" (match-string 1 expr))
(setq sig (verilog-string-remove-spaces (match-string 1 expr))
expr (substring expr (match-end 0)))))
- ;; Find [vector] or [multi][multi][multi][vector]
- (while (string-match "^\\s-*\\(\\[[^]]+\\]\\)" expr)
+ ;; Find [vector] or [multi][multi][multi][vector] or [vector[VEC2]]
+ ;; Unfortunately Emacs regexps don't allow matching bracket searches, so just 2 deep.
+ (while (string-match "^\\s-*\\(\\[\\([^][]+\\|\\[[^][]+\\]\\)*\\]\\)" expr)
;;(message "vrsde-v: `%s'" (match-string 1 expr))
(when vec (setq multidim (cons vec multidim)))
(setq vec (match-string 1 expr)
@@ -8908,7 +8915,7 @@ Inserts the list of signals found, using submodi to look up each port."
(verilog-string-remove-spaces (match-string-no-properties 1)) ; sig
nil nil nil)) ; vec multidim mem
;;
- ((looking-at "\\([a-zA-Z_][a-zA-Z_0-9]*\\)\\s-*\\(\\[[^]]+\\]\\)\\s-*)")
+ ((looking-at "\\([a-zA-Z_][a-zA-Z_0-9]*\\)\\s-*\\(\\[[^][]+\\]\\)\\s-*)")
(verilog-read-sub-decls-sig
submoddecls par-values comment port
(verilog-string-remove-spaces (match-string-no-properties 1)) ; sig
@@ -8924,7 +8931,7 @@ Inserts the list of signals found, using submodi to look up each port."
(point)))))))) ; expr
;;
(forward-line 1)))))
-;;(verilog-read-sub-decls-line (verilog-subdecls-new nil nil nil nil nil) nil "Cmt")
+;;(verilog-read-sub-decls-line (verilog-decls-new nil nil nil nil nil nil nil nil nil) nil "Cmt")
(defun verilog-read-sub-decls-gate (submoddecls par-values comment submod end-inst-point)
"For `verilog-read-sub-decls', read lines of UDP gate decl until none match.
@@ -8951,7 +8958,7 @@ Inserts the list of signals found."
iolist (cdr iolist))
(verilog-read-sub-decls-expr
submoddecls par-values comment "primitive_port"
- (match-string 0)))
+ (match-string-no-properties 0)))
(t
(forward-char 1)
(skip-syntax-forward " ")))))))
@@ -8995,7 +9002,7 @@ Outputs comments above subcell signals, for example:
submodi submoddecls)
(cond
(subprim
- (setq submodi `primitive
+ (setq submodi 'primitive
submoddecls (verilog-decls-new nil nil nil nil nil nil nil nil nil)
comment (concat inst " of " submod))
(verilog-backward-open-paren)
@@ -9048,7 +9055,7 @@ For example if declare A A (.B(SIG)) then B will be included in the list."
pins pin)
(verilog-backward-open-paren)
(while (re-search-forward "\\.\\([^(,) \t\n\f]*\\)\\s-*" end-mod-point t)
- (setq pin (match-string 1))
+ (setq pin (match-string-no-properties 1))
(unless (verilog-inside-comment-or-string-p)
(setq pins (cons (list pin) pins))
(when (looking-at "(")
@@ -9062,7 +9069,7 @@ For example if declare A A (.B(SIG)) then B will be included in the list."
pins pin)
(verilog-backward-open-paren)
(while (re-search-forward "\\([a-zA-Z0-9$_.%`]+\\)" end-mod-point t)
- (setq pin (match-string 1))
+ (setq pin (match-string-no-properties 1))
(unless (verilog-inside-comment-or-string-p)
(setq pins (cons (list pin) pins))))
(vector pins))))
@@ -9083,7 +9090,7 @@ For example if declare A A (.B(SIG)) then B will be included in the list."
(backward-char 1)
(point)))
(while (re-search-forward "\\s-*\\([\"a-zA-Z0-9$_.%`]+\\)\\s-*,*" tpl-end-pt t)
- (setq sig-list (cons (list (match-string 1) nil nil) sig-list))))
+ (setq sig-list (cons (list (match-string-no-properties 1) nil nil) sig-list))))
sig-list)))
(defvar verilog-cache-has-lisp nil "True if any AUTO_LISP in buffer.")
@@ -9115,7 +9122,7 @@ Must call `verilog-read-auto-lisp-present' before this function."
"Recursive routine for parentheses/bracket matching.
EXIT-KEYWD is expression to stop at, nil if top level.
RVALUE is true if at right hand side of equal.
-IGNORE-NEXT is true to ignore next token, fake from inside case statement."
+TEMP-NEXT is true to ignore next token, fake from inside case statement."
(let* ((semi-rvalue (equal "endcase" exit-keywd)) ; true if after a ; we are looking for rvalue
keywd last-keywd sig-tolk sig-last-tolk gotend got-sig got-list end-else-check
ignore-next)
@@ -9154,7 +9161,9 @@ IGNORE-NEXT is true to ignore next token, fake from inside case statement."
;;(if dbg (setq dbg (concat dbg (format "\tif-check-else-other %s\n" keywd))))
(setq gotend t))
;; Final statement?
- ((and exit-keywd (and (equal keywd exit-keywd)
+ ((and exit-keywd (and (or (equal keywd exit-keywd)
+ (and (equal exit-keywd "'}")
+ (equal keywd "}")))
(not (looking-at "::"))))
(setq gotend t)
(forward-char (length keywd)))
@@ -9167,9 +9176,13 @@ IGNORE-NEXT is true to ignore next token, fake from inside case statement."
(setq end-else-check t))
(forward-char 1))
((equal keywd "'")
- (if (looking-at "'[sS]?[hdxboHDXBO]?[ \t]*[0-9a-fA-F_xzXZ?]+")
- (goto-char (match-end 0))
- (forward-char 1)))
+ (cond ((looking-at "'[sS]?[hdxboHDXBO]?[ \t]*[0-9a-fA-F_xzXZ?]+")
+ (goto-char (match-end 0)))
+ ((looking-at "'{")
+ (forward-char 2)
+ (verilog-read-always-signals-recurse "'}" t nil))
+ (t
+ (forward-char 1))))
((equal keywd ":") ; Case statement, begin/end label, x?y:z
(cond ((looking-at "::")
(forward-char 1)) ; Another forward-char below
@@ -9179,6 +9192,8 @@ IGNORE-NEXT is true to ignore next token, fake from inside case statement."
) ; NOP
((equal "]" exit-keywd) ; [x:y] rvalue
) ; NOP
+ ((equal "'}" exit-keywd) ; Pattern assignment
+ ) ; NOP
(got-sig ; label: statement
(setq ignore-next nil rvalue semi-rvalue got-sig nil))
((not rvalue) ; begin label
@@ -9289,9 +9304,8 @@ IGNORE-NEXT is true to ignore next token, fake from inside case statement."
(forward-line 1))
(beginning-of-line)
(if (looking-at "^\\s-*\\([a-zA-Z0-9`_$]+\\)\\s-+\\([a-zA-Z0-9`_$]+\\)\\s-*(")
- ;;(if (looking-at "^\\(.+\\)$")
- (let ((module (match-string 1))
- (instant (match-string 2)))
+ (let ((module (match-string-no-properties 1))
+ (instant (match-string-no-properties 2)))
(if (not (member module verilog-keywords))
(setq instants-list (cons (list module instant) instants-list)))))
(forward-line 1)))
@@ -9311,7 +9325,7 @@ Returns REGEXP and list of ( (signal_name connection_name)... )."
;; We reserve @"..." for future lisp expressions that evaluate
;; once-per-AUTOINST
(when (looking-at "\\s-*\"\\([^\"]*\\)\"")
- (setq tpl-regexp (match-string 1))
+ (setq tpl-regexp (match-string-no-properties 1))
(goto-char (match-end 0)))
(search-forward "(")
;; Parse lines in the template
@@ -9508,8 +9522,8 @@ warning message, you need to add to your init file:
(when recurse
(goto-char (point-min))
(while (re-search-forward "^\\s-*`include\\s-+\\([^ \t\n\f]+\\)" nil t)
- (let ((inc (verilog-string-replace-matches
- "\"" "" nil nil (match-string-no-properties 1))))
+ (let ((inc (verilog-substitute-include-name
+ (match-string-no-properties 1))))
(unless (verilog-inside-comment-or-string-p)
(verilog-read-defines inc recurse t)))))
;; Read `defines
@@ -9581,7 +9595,8 @@ foo.v (an include file):
(verilog-getopt-flags)
(goto-char (point-min))
(while (re-search-forward "^\\s-*`include\\s-+\\([^ \t\n\f]+\\)" nil t)
- (let ((inc (verilog-string-replace-matches "\"" "" nil nil (match-string 1))))
+ (let ((inc (verilog-substitute-include-name
+ (match-string-no-properties 1))))
(verilog-read-defines inc nil t)))))
(defun verilog-read-signals (&optional start end)
@@ -9650,7 +9665,7 @@ Use DEFAULT-DIR to anchor paths if non-nil."
((string-match "^\\+libext\\+\\(.*\\)" arg)
(setq arg (match-string 1 arg))
(while (string-match "\\([^+]+\\)\\+?\\(.*\\)" arg)
- (verilog-add-list-unique `verilog-library-extensions
+ (verilog-add-list-unique 'verilog-library-extensions
(match-string 1 arg))
(setq arg (match-string 2 arg))))
;;
@@ -9662,7 +9677,7 @@ Use DEFAULT-DIR to anchor paths if non-nil."
;;
((or (string-match "^\\+incdir\\+\\(.*\\)" arg) ; +incdir+dir
(string-match "^-I\\(.*\\)" arg)) ; -Idir
- (verilog-add-list-unique `verilog-library-directories
+ (verilog-add-list-unique 'verilog-library-directories
(substitute-in-file-name (match-string 1 arg))))
;; Ignore
((equal "+librescan" arg))
@@ -9677,15 +9692,15 @@ Use DEFAULT-DIR to anchor paths if non-nil."
(verilog-getopt-file (verilog-substitute-file-name-path arg default-dir) nil))
((equal next-param "-v")
(setq next-param nil)
- (verilog-add-list-unique `verilog-library-files
+ (verilog-add-list-unique 'verilog-library-files
(verilog-substitute-file-name-path arg default-dir)))
((equal next-param "-y")
(setq next-param nil)
- (verilog-add-list-unique `verilog-library-directories
+ (verilog-add-list-unique 'verilog-library-directories
(verilog-substitute-file-name-path arg default-dir)))
;; Filename
((string-match "^[^-+]" arg)
- (verilog-add-list-unique `verilog-library-files
+ (verilog-add-list-unique 'verilog-library-files
(verilog-substitute-file-name-path arg default-dir)))
;; Default - ignore; no warning
))))
@@ -9714,7 +9729,7 @@ Use DEFAULT-DIR to anchor paths if non-nil."
(defun verilog-getopt-flags ()
"Convert `verilog-library-flags' into standard library variables."
;; If the flags are local, then all the outputs should be local also
- (when (local-variable-p `verilog-library-flags (current-buffer))
+ (when (local-variable-p 'verilog-library-flags (current-buffer))
(mapc 'make-local-variable '(verilog-library-extensions
verilog-library-directories
verilog-library-files
@@ -9733,6 +9748,12 @@ Use DEFAULT-DIR to anchor paths if non-nil."
(expand-file-name (substitute-in-file-name filename) default-dir)
(substitute-in-file-name filename)))
+(defun verilog-substitute-include-name (filename)
+ "Return FILENAME for include with define substituted."
+ (setq filename (verilog-string-replace-matches "\"" "" nil nil filename))
+ (verilog-string-replace-matches "\"" "" nil nil
+ (verilog-symbol-detick filename t)))
+
(defun verilog-add-list-unique (varref object)
"Append to VARREF list the given OBJECT,
unless it is already a member of the variable's list."
@@ -9744,10 +9765,10 @@ unless it is already a member of the variable's list."
(defun verilog-current-flags ()
"Convert `verilog-library-flags' and similar variables to command line.
Used for __FLAGS__ in `verilog-expand-command'."
- (let ((cmd (mapconcat `concat verilog-library-flags " ")))
+ (let ((cmd (mapconcat #'concat verilog-library-flags " ")))
(when (equal cmd "")
(setq cmd (concat
- "+libext+" (mapconcat `concat verilog-library-extensions "+")
+ "+libext+" (mapconcat #'concat verilog-library-extensions "+")
(mapconcat (lambda (i) (concat " -y " i " +incdir+" i))
verilog-library-directories "")
(mapconcat (lambda (i) (concat " -v " i))
@@ -9886,7 +9907,8 @@ If undefined, and WING-IT, return just SYMBOL without the tick, else nil."
(defun verilog-symbol-detick-text (text)
"Return TEXT without any known defines.
-If the variable vh-{symbol} is defined, substitute that value."
+If the variable vh-{symbol} is defined, substitute that value.
+This function is intended for use in AUTO_TEMPLATE Lisp expressions."
(let ((ok t) symbol val)
(while (and ok (string-match "`\\([a-zA-Z0-9_]+\\)" text))
(setq symbol (match-string 1 text))
@@ -9972,7 +9994,7 @@ variables to build the path. With optional CHECK-EXT also check
(while chkdirs
(setq chkdir (expand-file-name (car chkdirs)
(file-name-directory current))
- chkexts (if check-ext verilog-library-extensions `("")))
+ chkexts (if check-ext verilog-library-extensions '("")))
(while chkexts
(setq fn (expand-file-name (concat filename (car chkexts))
chkdir))
@@ -10131,7 +10153,7 @@ Return modi if successful, else print message unless IGNORE-ERROR is true."
(set-buffer (if (bufferp (verilog-modi-file-or-buffer modi))
(verilog-modi-file-or-buffer modi)
(find-file-noselect (verilog-modi-file-or-buffer modi))))
- (or (equal major-mode `verilog-mode) ; Put into Verilog mode to get syntax
+ (or (equal major-mode 'verilog-mode) ; Put into Verilog mode to get syntax
(verilog-mode))
(goto-char (verilog-modi-get-point modi)))
@@ -10402,7 +10424,7 @@ When MODI is non-null, also add to modi-cache, for tracking."
(t
(error "Unsupported verilog-insert-definition direction: `%s'" direction))))
(or dont-sort
- (setq sigs (sort (copy-alist sigs) `verilog-signals-sort-compare)))
+ (setq sigs (sort (copy-alist sigs) #'verilog-signals-sort-compare)))
(while sigs
(let ((sig (car sigs)))
(verilog-insert-one-definition
@@ -10518,67 +10540,96 @@ This repairs those mis-inserted by an AUTOARG."
(defun verilog-simplify-range-expression (expr)
"Return a simplified range expression with constants eliminated from EXPR."
;; Note this is always called with brackets; ie [z] or [z:z]
- (if (not (string-match "[---+*()]" expr))
- expr ; short-circuit
+ (if (or (not verilog-auto-simplify-expressions)
+ (not (string-match "[---+*/<>()]" expr)))
+ expr ; disabled or short-circuited
(let ((out expr)
(last-pass ""))
(while (not (equal last-pass out))
- (setq last-pass out)
- ;; Prefix regexp needs beginning of match, or some symbol of
- ;; lesser or equal precedence. We assume the [:]'s exist in expr.
- ;; Ditto the end.
- (while (string-match
- (concat "\\([[({:*+-]\\)" ; - must be last
- "(\\<\\([0-9A-Za-z_]+\\))"
- "\\([])}:*+-]\\)")
- out)
- (setq out (replace-match "\\1\\2\\3" nil nil out)))
- (while (string-match
- (concat "\\([[({:*+-]\\)" ; - must be last
- "\\$clog2\\s *(\\<\\([0-9]+\\))"
- "\\([])}:*+-]\\)")
- out)
- (setq out (replace-match
- (concat
- (match-string 1 out)
- (int-to-string (verilog-clog2 (string-to-number (match-string 2 out))))
- (match-string 3 out))
- nil nil out)))
- ;; For precedence do * before +/-
- (while (string-match
- (concat "\\([[({:*+-]\\)"
- "\\([0-9]+\\)\\s *\\([*]\\)\\s *\\([0-9]+\\)"
- "\\([])}:*+-]\\)")
- out)
- (setq out (replace-match
- (concat (match-string 1 out)
- (int-to-string (* (string-to-number (match-string 2 out))
- (string-to-number (match-string 4 out))))
- (match-string 5 out))
- nil nil out)))
- (while (string-match
- (concat "\\([[({:+-]\\)" ; No * here as higher prec
- "\\([0-9]+\\)\\s *\\([---+]\\)\\s *\\([0-9]+\\)"
- "\\([])}:+-]\\)")
- out)
- (let ((pre (match-string 1 out))
- (lhs (string-to-number (match-string 2 out)))
- (rhs (string-to-number (match-string 4 out)))
- (post (match-string 5 out))
- val)
- (when (equal pre "-")
- (setq lhs (- lhs)))
- (setq val (if (equal (match-string 3 out) "-")
- (- lhs rhs)
- (+ lhs rhs))
- out (replace-match
- (concat (if (and (equal pre "-")
- (< val 0))
- "" ; Not "--20" but just "-20"
- pre)
- (int-to-string val)
- post)
- nil nil out)) )))
+ (while (not (equal last-pass out))
+ (setq last-pass out)
+ ;; Prefix regexp needs beginning of match, or some symbol of
+ ;; lesser or equal precedence. We assume the [:]'s exist in expr.
+ ;; Ditto the end.
+ (while (string-match
+ (concat "\\([[({:*/<>+-]\\)" ; - must be last
+ "(\\<\\([0-9A-Za-z_]+\\))"
+ "\\([])}:*/<>+-]\\)")
+ out)
+ (setq out (replace-match "\\1\\2\\3" nil nil out)))
+ (while (string-match
+ (concat "\\([[({:*/<>+-]\\)" ; - must be last
+ "\\$clog2\\s *(\\<\\([0-9]+\\))"
+ "\\([])}:*/<>+-]\\)")
+ out)
+ (setq out (replace-match
+ (concat
+ (match-string 1 out)
+ (int-to-string (verilog-clog2 (string-to-number (match-string 2 out))))
+ (match-string 3 out))
+ nil nil out)))
+ ;; For precedence do *,/ before +,-,>>,<<
+ (while (string-match
+ (concat "\\([[({:*/<>+-]\\)"
+ "\\([0-9]+\\)\\s *\\([*/]\\)\\s *\\([0-9]+\\)"
+ "\\([])}:*/<>+-]\\)")
+ out)
+ (setq out (replace-match
+ (concat (match-string 1 out)
+ (if (equal (match-string 3 out) "/")
+ (int-to-string (/ (string-to-number (match-string 2 out))
+ (string-to-number (match-string 4 out)))))
+ (if (equal (match-string 3 out) "*")
+ (int-to-string (* (string-to-number (match-string 2 out))
+ (string-to-number (match-string 4 out)))))
+ (match-string 5 out))
+ nil nil out)))
+ ;; Next precedence is +,-
+ (while (string-match
+ (concat "\\([[({:<>+-]\\)" ; No *,/ here as higher prec
+ "\\([0-9]+\\)\\s *\\([---+]\\)\\s *\\([0-9]+\\)"
+ "\\([])}:<>+-]\\)")
+ out)
+ (let ((pre (match-string 1 out))
+ (lhs (string-to-number (match-string 2 out)))
+ (rhs (string-to-number (match-string 4 out)))
+ (post (match-string 5 out))
+ val)
+ (when (equal pre "-")
+ (setq lhs (- lhs)))
+ (setq val (if (equal (match-string 3 out) "-")
+ (- lhs rhs)
+ (+ lhs rhs))
+ out (replace-match
+ (concat (if (and (equal pre "-")
+ (< val 0))
+ "" ; Not "--20" but just "-20"
+ pre)
+ (int-to-string val)
+ post)
+ nil nil out)) ))
+ ;; Next precedence is >>,<<
+ (while (string-match
+ (concat "\\([[({:]\\)" ;; No << as not transitive
+ "\\([0-9]+\\)\\s *\\([<]\\{2,3\\}\\|[>]\\{2,3\\}\\)\\s *\\([0-9]+\\)"
+ "\\([])}:<>]\\)")
+ out)
+ (setq out (replace-match
+ (concat (match-string 1 out)
+ (if (equal (match-string 3 out) ">>")
+ (int-to-string (lsh (string-to-number (match-string 2 out))
+ (* -1 (string-to-number (match-string 4 out))))))
+ (if (equal (match-string 3 out) "<<")
+ (int-to-string (lsh (string-to-number (match-string 2 out))
+ (string-to-number (match-string 4 out)))))
+ (if (equal (match-string 3 out) ">>>")
+ (int-to-string (ash (string-to-number (match-string 2 out))
+ (* -1 (string-to-number (match-string 4 out))))))
+ (if (equal (match-string 3 out) "<<<")
+ (int-to-string (ash (string-to-number (match-string 2 out))
+ (string-to-number (match-string 4 out)))))
+ (match-string 5 out))
+ nil nil out)))))
out)))
;;(verilog-simplify-range-expression "[1:3]") ; 1
@@ -10591,6 +10642,9 @@ This repairs those mis-inserted by an AUTOARG."
;;(verilog-simplify-range-expression "[FOO-1+1-1+1]") ; FOO-0
;;(verilog-simplify-range-expression "[$clog2(2)]") ; 1
;;(verilog-simplify-range-expression "[$clog2(7)]") ; 3
+;;(verilog-simplify-range-expression "[(TEST[1])-1:0]")
+;;(verilog-simplify-range-expression "[1<<2:8>>2]") ; [4:2]
+;;(verilog-simplify-range-expression "[2*4/(4-2) +2+4 <<4 >>2]")
(defun verilog-clog2 (value)
"Compute $clog2 - ceiling log2 of VALUE."
@@ -10746,7 +10800,7 @@ Intended for internal use inside a `verilog-save-font-no-change-functions' block
(concat "/\\*"
(eval-when-compile
(verilog-regexp-words
- `("AS" "AUTOARG" "AUTOCONCATWIDTH" "AUTOINST" "AUTOINSTPARAM"
+ '("AS" "AUTOARG" "AUTOCONCATWIDTH" "AUTOINST" "AUTOINSTPARAM"
"AUTOSENSE")))
"\\*/")
'verilog-delete-to-paren)
@@ -11018,8 +11072,7 @@ or `diff' in batch mode."
(progn
(with-current-buffer b1 (setq buffer-file-name nil))
(verilog-auto)
- (when (not verilog-auto-star-save)
- (verilog-delete-auto-star-implicit)))
+ (verilog-star-cleanup))
;; Restore name if unwind
(with-current-buffer b1 (setq buffer-file-name name1)))))
;;
@@ -11036,6 +11089,11 @@ or `diff' in batch mode."
;; Auto save
;;
+(defun verilog-star-cleanup ()
+ "On saving or diff, cleanup .* expansions."
+ (when (not verilog-auto-star-save)
+ (verilog-delete-auto-star-implicit)))
+
(defun verilog-auto-save-check ()
"On saving see if we need auto update."
(cond ((not verilog-auto-save-policy)) ; disabled
@@ -11055,8 +11113,7 @@ or `diff' in batch mode."
(verilog-auto))
;; Don't ask again if didn't update
(set (make-local-variable 'verilog-auto-update-tick) (buffer-chars-modified-tick))))
- (when (not verilog-auto-star-save)
- (verilog-delete-auto-star-implicit))
+ (verilog-star-cleanup)
nil) ; Always return nil -- we don't write the file ourselves
(defun verilog-auto-read-locals ()
@@ -11087,7 +11144,7 @@ If FORCE, always reread it."
Takes SIGS list, adds MESSAGE to front and inserts each at INDENT-PT."
(when sigs
(when verilog-auto-arg-sort
- (setq sigs (sort (copy-alist sigs) `verilog-signals-sort-compare)))
+ (setq sigs (sort (copy-alist sigs) #'verilog-signals-sort-compare)))
(insert "\n")
(indent-to indent-pt)
(insert message)
@@ -11241,8 +11298,8 @@ See the example in `verilog-auto-inout-modport'."
(verilog-signals-matching-dir-re
(verilog-signals-matching-regexp sig-list-o regexp)
"output" direction-re)))
- (setq sig-list-i (sort (copy-alist sig-list-i) `verilog-signals-sort-compare))
- (setq sig-list-o (sort (copy-alist sig-list-o) `verilog-signals-sort-compare))
+ (setq sig-list-i (sort (copy-alist sig-list-i) #'verilog-signals-sort-compare))
+ (setq sig-list-o (sort (copy-alist sig-list-o) #'verilog-signals-sort-compare))
(when (or sig-list-i sig-list-o)
(verilog-insert-indent "// Beginning of automatic assignments from modport\n")
;; Don't sort them so an upper AUTOINST will match the main module
@@ -11386,7 +11443,7 @@ If PAR-VALUES replace final strings with these parameter values."
(indent-to (+ (if (< verilog-auto-inst-column 48) 24 16)
verilog-auto-inst-column))
;; verilog-insert requires the complete comment in one call - including the newline
- (cond ((equal verilog-auto-inst-template-numbers `lhs)
+ (cond ((equal verilog-auto-inst-template-numbers 'lhs)
(verilog-insert " // Templated"
" LHS: " (nth 0 tpl-ass)
"\n"))
@@ -11410,7 +11467,7 @@ If PAR-VALUES replace final strings with these parameter values."
(defun verilog-auto-inst-port-list (sig-list indent-pt moddecls tpl-list tpl-num for-star par-values)
"For `verilog-auto-inst' print a list of ports using `verilog-auto-inst-port'."
(when verilog-auto-inst-sort
- (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare)))
+ (setq sig-list (sort (copy-alist sig-list) #'verilog-signals-sort-compare)))
(mapc (lambda (port)
(verilog-auto-inst-port port indent-pt moddecls
tpl-list tpl-num for-star par-values))
@@ -12252,7 +12309,7 @@ same expansion will result from only extracting outputs starting with ov:
"Expand AUTOOUTPUTEVERY statements, as part of \\[verilog-auto].
Make output statements for any signals that aren't primary inputs or
outputs already. This makes every signal in the design an output. This is
-useful to get Synopsys to preserve every signal in the design, since it
+useful to get synthesis to preserve every signal in the design, since it
won't optimize away the outputs.
An example:
@@ -13108,7 +13165,7 @@ operator. (This was added to the language in part due to AUTOSENSE!)
(verilog-re-search-backward-quick "\\s-" start-pt t))
(not (looking-at "\\s-or\\b"))))
(setq not-first t))
- (setq sig-list (sort sig-list `verilog-signals-sort-compare))
+ (setq sig-list (sort sig-list #'verilog-signals-sort-compare))
(while sig-list
(cond ((> (+ 4 (current-column) (length (verilog-sig-name (car sig-list)))) fill-column) ;+4 for width of or
(insert "\n")
@@ -13217,7 +13274,7 @@ Typing \\[verilog-auto] will make this into:
(append
(verilog-alw-get-temps sigss)
prereset-sigs)))
- (setq sig-list (sort sig-list `verilog-signals-sort-compare))
+ (setq sig-list (sort sig-list #'verilog-signals-sort-compare))
(when sig-list
(insert "\n");
(verilog-insert-indent "// Beginning of autoreset for uninitialized flops\n");
@@ -13308,7 +13365,7 @@ Typing \\[verilog-auto] will make this into:
(when sig-list
(verilog-forward-or-insert-line)
(verilog-insert-indent "// Beginning of automatic tieoffs (for this module's unterminated outputs)\n")
- (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare))
+ (setq sig-list (sort (copy-alist sig-list) #'verilog-signals-sort-compare))
(verilog-modi-cache-add-vars modi sig-list) ; Before we trash list
(while sig-list
(let ((sig (car sig-list)))
@@ -13461,7 +13518,7 @@ Typing \\[verilog-auto] will make this into:
(when sig-list
(verilog-forward-or-insert-line)
(verilog-insert-indent "// Beginning of automatic unused inputs\n")
- (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare))
+ (setq sig-list (sort (copy-alist sig-list) #'verilog-signals-sort-compare))
(while sig-list
(let ((sig (car sig-list)))
(indent-to indent-pt)
@@ -13510,19 +13567,19 @@ Finally, an AUTOASCIIENUM command is used.
`verilog-auto-wire-type' may be used to change the datatype of
the declarations.
- \"auto enum\" may be used in place of \"synopsys enum\".
+ \"synopsys enum\" may be used in place of \"auto enum\".
An example:
//== State enumeration
- parameter [2:0] // synopsys enum state_info
+ parameter [2:0] // auto enum state_info
SM_IDLE = 3\\='b000,
SM_SEND = 3\\='b001,
SM_WAIT1 = 3\\='b010;
//== State variables
- reg [2:0] /* synopsys enum state_info */
- state_r; /* synopsys state_vector state_r */
- reg [2:0] /* synopsys enum state_info */
+ reg [2:0] /* auto enum state_info */
+ state_r; /* auto state_vector state_r */
+ reg [2:0] /* auto enum state_info */
state_e1;
/*AUTOASCIIENUM(\"state_r\", \"state_ascii_r\", \"SM_\")*/
@@ -13654,9 +13711,11 @@ being different from the final output's line numbering."
(while (re-search-forward " Templated T\\([0-9]+\\) L\\([0-9]+\\)" nil t)
(replace-match
(concat " Templated "
- (int-to-string (+ (nth (string-to-number (match-string 1))
+ (int-to-string (+ (nth (string-to-number
+ (match-string-no-properties 1))
template-line)
- (string-to-number (match-string 2)))))
+ (string-to-number
+ (match-string-no-properties 2)))))
t t))))
(defun verilog-auto-template-lint ()
@@ -13787,7 +13846,7 @@ Wilson Snyder (wsnyder@wsnyder.org)."
;; Local state
(verilog-read-auto-template-init)
;; If we're not in verilog-mode, change syntax table so parsing works right
- (unless (eq major-mode `verilog-mode) (verilog-mode))
+ (unless (eq major-mode 'verilog-mode) (verilog-mode))
;; Allow user to customize
(verilog-run-hooks 'verilog-before-auto-hook)
;; Try to save the user from needing to revert-file to reread file local-variables
@@ -14418,11 +14477,14 @@ Files are checked based on `verilog-library-flags'."
(when (and (not hit)
(looking-at verilog-include-file-regexp))
(if (and (car (verilog-library-filenames
- (match-string 1) (buffer-file-name)))
+ (match-string-no-properties 1)
+ (buffer-file-name)))
(file-readable-p (car (verilog-library-filenames
- (match-string 1) (buffer-file-name)))))
+ (match-string-no-properties 1)
+ (buffer-file-name)))))
(find-file (car (verilog-library-filenames
- (match-string 1) (buffer-file-name))))
+ (match-string-no-properties 1)
+ (buffer-file-name))))
(when warn
(message
"File `%s' isn't readable, use shift-mouse2 to paste in this field"
@@ -14507,7 +14569,6 @@ Files are checked based on `verilog-library-flags'."
verilog-highlight-grouping-keywords
verilog-highlight-includes
verilog-highlight-modules
- verilog-highlight-p1800-keywords
verilog-highlight-translate-off
verilog-indent-begin-after-if
verilog-indent-declaration-macros
generated by cgit v1.2.3 (git 2.39.1) at 2025-04-27 14:49:44 +0000