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| author | Thomas Lively <7121787+tlively@users.noreply.github.com> | 2020-12-11 19:06:34 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-12-11 19:06:34 -0500 |
| commit | dd33ae0512aa97f537d40e61631d268c8a8fd17e (patch) | |
| tree | e5c219ba349e56940669bb873bb57a3f2626bf77 /scripts/gen-s-parser.py | |
| parent | 290147d8d43a7448d68939ec711b524ba4fb3fbd (diff) | |
| download | binaryen-dd33ae0512aa97f537d40e61631d268c8a8fd17e.tar.gz binaryen-dd33ae0512aa97f537d40e61631d268c8a8fd17e.tar.bz2 binaryen-dd33ae0512aa97f537d40e61631d268c8a8fd17e.zip | |
Prototype SIMD instructions implemented in LLVM (#3440)
- i64x2.eq (https://github.com/WebAssembly/simd/pull/381)
- i64x2 widens (https://github.com/WebAssembly/simd/pull/290)
- i64x2.bitmask (https://github.com/WebAssembly/simd/pull/368)
- signselect ops (https://github.com/WebAssembly/simd/pull/124)
Diffstat (limited to 'scripts/gen-s-parser.py')
| -rwxr-xr-x | scripts/gen-s-parser.py | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/scripts/gen-s-parser.py b/scripts/gen-s-parser.py index e94c58086..545d48f9c 100755 --- a/scripts/gen-s-parser.py +++ b/scripts/gen-s-parser.py @@ -332,6 +332,7 @@ instructions = [ ("i32x4.le_u", "makeBinary(s, BinaryOp::LeUVecI32x4)"), ("i32x4.ge_s", "makeBinary(s, BinaryOp::GeSVecI32x4)"), ("i32x4.ge_u", "makeBinary(s, BinaryOp::GeUVecI32x4)"), + ("i64x2.eq", "makeBinary(s, BinaryOp::EqVecI64x2)"), ("f32x4.eq", "makeBinary(s, BinaryOp::EqVecF32x4)"), ("f32x4.ne", "makeBinary(s, BinaryOp::NeVecF32x4)"), ("f32x4.lt", "makeBinary(s, BinaryOp::LtVecF32x4)"), @@ -350,6 +351,10 @@ instructions = [ ("v128.xor", "makeBinary(s, BinaryOp::XorVec128)"), ("v128.andnot", "makeBinary(s, BinaryOp::AndNotVec128)"), ("v128.bitselect", "makeSIMDTernary(s, SIMDTernaryOp::Bitselect)"), + ("v8x16.signselect", "makeSIMDTernary(s, SIMDTernaryOp::SignSelectVec8x16)"), + ("v16x8.signselect", "makeSIMDTernary(s, SIMDTernaryOp::SignSelectVec16x8)"), + ("v32x4.signselect", "makeSIMDTernary(s, SIMDTernaryOp::SignSelectVec32x4)"), + ("v64x2.signselect", "makeSIMDTernary(s, SIMDTernaryOp::SignSelectVec64x2)"), ("v128.load8_lane", "makeSIMDLoadStoreLane(s, LoadLaneVec8x16)"), ("v128.load16_lane", "makeSIMDLoadStoreLane(s, LoadLaneVec16x8)"), ("v128.load32_lane", "makeSIMDLoadStoreLane(s, LoadLaneVec32x4)"), @@ -427,6 +432,7 @@ instructions = [ ("i64x2.neg", "makeUnary(s, UnaryOp::NegVecI64x2)"), ("i64x2.any_true", "makeUnary(s, UnaryOp::AnyTrueVecI64x2)"), ("i64x2.all_true", "makeUnary(s, UnaryOp::AllTrueVecI64x2)"), + ("i64x2.bitmask", "makeUnary(s, UnaryOp::BitmaskVecI64x2)"), ("i64x2.shl", "makeSIMDShift(s, SIMDShiftOp::ShlVecI64x2)"), ("i64x2.shr_s", "makeSIMDShift(s, SIMDShiftOp::ShrSVecI64x2)"), ("i64x2.shr_u", "makeSIMDShift(s, SIMDShiftOp::ShrUVecI64x2)"), @@ -503,6 +509,10 @@ instructions = [ ("i32x4.widen_high_i16x8_s", "makeUnary(s, UnaryOp::WidenHighSVecI16x8ToVecI32x4)"), ("i32x4.widen_low_i16x8_u", "makeUnary(s, UnaryOp::WidenLowUVecI16x8ToVecI32x4)"), ("i32x4.widen_high_i16x8_u", "makeUnary(s, UnaryOp::WidenHighUVecI16x8ToVecI32x4)"), + ("i64x2.widen_low_i32x4_s", "makeUnary(s, UnaryOp::WidenLowSVecI32x4ToVecI64x2)"), + ("i64x2.widen_high_i32x4_s", "makeUnary(s, UnaryOp::WidenHighSVecI32x4ToVecI64x2)"), + ("i64x2.widen_low_i32x4_u", "makeUnary(s, UnaryOp::WidenLowUVecI32x4ToVecI64x2)"), + ("i64x2.widen_high_i32x4_u", "makeUnary(s, UnaryOp::WidenHighUVecI32x4ToVecI64x2)"), ("v8x16.swizzle", "makeBinary(s, BinaryOp::SwizzleVec8x16)"), # reference types instructions # TODO Add table instructions |