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authorThomas Lively <7121787+tlively@users.noreply.github.com>2019-09-24 15:29:15 -0700
committerGitHub <noreply@github.com>2019-09-24 15:29:15 -0700
commit034ed383a968204427befda3f9fb8bb5d2f63f75 (patch)
tree36ae37db02cdae27416be250fe533d0f0bff77e8 /scripts
parent835581f58eb5040656243f7345ebcacf6d7deee5 (diff)
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v128.andnot instruction (#2355)
As specified at https://github.com/WebAssembly/simd/pull/102. Also fixes bugs in the JS API for other SIMD bitwise operators.
Diffstat (limited to 'scripts')
-rwxr-xr-xscripts/gen-s-parser.py1
1 files changed, 1 insertions, 0 deletions
diff --git a/scripts/gen-s-parser.py b/scripts/gen-s-parser.py
index f00a18db9..acb76a176 100755
--- a/scripts/gen-s-parser.py
+++ b/scripts/gen-s-parser.py
@@ -355,6 +355,7 @@ instructions = [
("v128.and", "makeBinary(s, BinaryOp::AndVec128)"),
("v128.or", "makeBinary(s, BinaryOp::OrVec128)"),
("v128.xor", "makeBinary(s, BinaryOp::XorVec128)"),
+ ("v128.andnot", "makeBinary(s, BinaryOp::AndNotVec128)"),
("v128.bitselect", "makeSIMDTernary(s, SIMDTernaryOp::Bitselect)"),
("i8x16.neg", "makeUnary(s, UnaryOp::NegVecI8x16)"),
("i8x16.any_true", "makeUnary(s, UnaryOp::AnyTrueVecI8x16)"),