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| author | Thomas Lively <7121787+tlively@users.noreply.github.com> | 2020-03-20 16:31:16 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-03-20 16:31:16 -0700 |
| commit | 03ae7fcbfc5cedefd25c2414616cb1d3f77ab51b (patch) | |
| tree | 17f6a9148ffd659f870dfe5745383fb1507e4d42 /scripts | |
| parent | 39fda77da51f83b200fc63bbfbc4dd2ccbfc2388 (diff) | |
| download | binaryen-03ae7fcbfc5cedefd25c2414616cb1d3f77ab51b.tar.gz binaryen-03ae7fcbfc5cedefd25c2414616cb1d3f77ab51b.tar.bz2 binaryen-03ae7fcbfc5cedefd25c2414616cb1d3f77ab51b.zip | |
SIMD integer abs and bitmask instructions (#2703)
Adds full support for the {i8x16,i16x8,i32x4}.abs instructions merged
to the SIMD proposal in https://github.com/WebAssembly/simd/pull/128
as well as the {i8x16,i16x8,i32x4}.bitmask instructions proposed in
https://github.com/WebAssembly/simd/pull/201.
Diffstat (limited to 'scripts')
| -rwxr-xr-x | scripts/gen-s-parser.py | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/scripts/gen-s-parser.py b/scripts/gen-s-parser.py index e290322fb..cbc7307c8 100755 --- a/scripts/gen-s-parser.py +++ b/scripts/gen-s-parser.py @@ -360,9 +360,11 @@ instructions = [ ("v128.xor", "makeBinary(s, BinaryOp::XorVec128)"), ("v128.andnot", "makeBinary(s, BinaryOp::AndNotVec128)"), ("v128.bitselect", "makeSIMDTernary(s, SIMDTernaryOp::Bitselect)"), + ("i8x16.abs", "makeUnary(s, UnaryOp::AbsVecI8x16)"), ("i8x16.neg", "makeUnary(s, UnaryOp::NegVecI8x16)"), ("i8x16.any_true", "makeUnary(s, UnaryOp::AnyTrueVecI8x16)"), ("i8x16.all_true", "makeUnary(s, UnaryOp::AllTrueVecI8x16)"), + ("i8x16.bitmask", "makeUnary(s, UnaryOp::BitmaskVecI8x16)"), ("i8x16.shl", "makeSIMDShift(s, SIMDShiftOp::ShlVecI8x16)"), ("i8x16.shr_s", "makeSIMDShift(s, SIMDShiftOp::ShrSVecI8x16)"), ("i8x16.shr_u", "makeSIMDShift(s, SIMDShiftOp::ShrUVecI8x16)"), @@ -378,9 +380,11 @@ instructions = [ ("i8x16.max_s", "makeBinary(s, BinaryOp::MaxSVecI8x16)"), ("i8x16.max_u", "makeBinary(s, BinaryOp::MaxUVecI8x16)"), ("i8x16.avgr_u", "makeBinary(s, BinaryOp::AvgrUVecI8x16)"), + ("i16x8.abs", "makeUnary(s, UnaryOp::AbsVecI16x8)"), ("i16x8.neg", "makeUnary(s, UnaryOp::NegVecI16x8)"), ("i16x8.any_true", "makeUnary(s, UnaryOp::AnyTrueVecI16x8)"), ("i16x8.all_true", "makeUnary(s, UnaryOp::AllTrueVecI16x8)"), + ("i16x8.bitmask", "makeUnary(s, UnaryOp::BitmaskVecI16x8)"), ("i16x8.shl", "makeSIMDShift(s, SIMDShiftOp::ShlVecI16x8)"), ("i16x8.shr_s", "makeSIMDShift(s, SIMDShiftOp::ShrSVecI16x8)"), ("i16x8.shr_u", "makeSIMDShift(s, SIMDShiftOp::ShrUVecI16x8)"), @@ -396,9 +400,11 @@ instructions = [ ("i16x8.max_s", "makeBinary(s, BinaryOp::MaxSVecI16x8)"), ("i16x8.max_u", "makeBinary(s, BinaryOp::MaxUVecI16x8)"), ("i16x8.avgr_u", "makeBinary(s, BinaryOp::AvgrUVecI16x8)"), + ("i32x4.abs", "makeUnary(s, UnaryOp::AbsVecI32x4)"), ("i32x4.neg", "makeUnary(s, UnaryOp::NegVecI32x4)"), ("i32x4.any_true", "makeUnary(s, UnaryOp::AnyTrueVecI32x4)"), ("i32x4.all_true", "makeUnary(s, UnaryOp::AllTrueVecI32x4)"), + ("i32x4.bitmask", "makeUnary(s, UnaryOp::BitmaskVecI32x4)"), ("i32x4.shl", "makeSIMDShift(s, SIMDShiftOp::ShlVecI32x4)"), ("i32x4.shr_s", "makeSIMDShift(s, SIMDShiftOp::ShrSVecI32x4)"), ("i32x4.shr_u", "makeSIMDShift(s, SIMDShiftOp::ShrUVecI32x4)"), |