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| author | Daniel Wirtz <dcode@dcode.io> | 2021-04-12 22:22:16 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-04-12 22:22:16 +0200 |
| commit | 0d7dac2923f9164ca7f1450b6f394ef8fa9d8a68 (patch) | |
| tree | b5ecd1defc11d31c77ea9ab9236282c5a85f9f0a /scripts | |
| parent | 2e4c96fab93de97665648d4ae83164e177431ad8 (diff) | |
| download | binaryen-0d7dac2923f9164ca7f1450b6f394ef8fa9d8a68.tar.gz binaryen-0d7dac2923f9164ca7f1450b6f394ef8fa9d8a68.tar.bz2 binaryen-0d7dac2923f9164ca7f1450b6f394ef8fa9d8a68.zip | |
Rename SIMD extending load instructions (#3798)
Renames the SIMD instructions
* LoadExtSVec8x8ToVecI16x8 -> Load8x8SVec128
* LoadExtUVec8x8ToVecI16x8 -> Load8x8UVec128
* LoadExtSVec16x4ToVecI32x4 -> Load16x4SVec128
* LoadExtUVec16x4ToVecI32x4 -> Load16x4UVec128
* LoadExtSVec32x2ToVecI64x2 -> Load32x2SVec128
* LoadExtUVec32x2ToVecI64x2 -> Load32x2UVec128
Diffstat (limited to 'scripts')
| -rwxr-xr-x | scripts/gen-s-parser.py | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/scripts/gen-s-parser.py b/scripts/gen-s-parser.py index 3f3f3eaf3..2b4c57f80 100755 --- a/scripts/gen-s-parser.py +++ b/scripts/gen-s-parser.py @@ -479,12 +479,12 @@ instructions = [ ("v128.load16_splat", "makeSIMDLoad(s, SIMDLoadOp::Load16SplatVec128)"), ("v128.load32_splat", "makeSIMDLoad(s, SIMDLoadOp::Load32SplatVec128)"), ("v128.load64_splat", "makeSIMDLoad(s, SIMDLoadOp::Load64SplatVec128)"), - ("v128.load8x8_s", "makeSIMDLoad(s, SIMDLoadOp::LoadExtSVec8x8ToVecI16x8)"), - ("v128.load8x8_u", "makeSIMDLoad(s, SIMDLoadOp::LoadExtUVec8x8ToVecI16x8)"), - ("v128.load16x4_s", "makeSIMDLoad(s, SIMDLoadOp::LoadExtSVec16x4ToVecI32x4)"), - ("v128.load16x4_u", "makeSIMDLoad(s, SIMDLoadOp::LoadExtUVec16x4ToVecI32x4)"), - ("v128.load32x2_s", "makeSIMDLoad(s, SIMDLoadOp::LoadExtSVec32x2ToVecI64x2)"), - ("v128.load32x2_u", "makeSIMDLoad(s, SIMDLoadOp::LoadExtUVec32x2ToVecI64x2)"), + ("v128.load8x8_s", "makeSIMDLoad(s, SIMDLoadOp::Load8x8SVec128)"), + ("v128.load8x8_u", "makeSIMDLoad(s, SIMDLoadOp::Load8x8UVec128)"), + ("v128.load16x4_s", "makeSIMDLoad(s, SIMDLoadOp::Load16x4SVec128)"), + ("v128.load16x4_u", "makeSIMDLoad(s, SIMDLoadOp::Load16x4UVec128)"), + ("v128.load32x2_s", "makeSIMDLoad(s, SIMDLoadOp::Load32x2SVec128)"), + ("v128.load32x2_u", "makeSIMDLoad(s, SIMDLoadOp::Load32x2UVec128)"), ("v128.load32_zero", "makeSIMDLoad(s, SIMDLoadOp::Load32ZeroVec128)"), ("v128.load64_zero", "makeSIMDLoad(s, SIMDLoadOp::Load64ZeroVec128)"), ("i8x16.narrow_i16x8_s", "makeBinary(s, BinaryOp::NarrowSVecI16x8ToVecI8x16)"), |