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| author | Thomas Lively <7121787+tlively@users.noreply.github.com> | 2019-09-03 14:13:29 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-09-03 14:13:29 -0700 |
| commit | 0faa68b9dfbe478c6d238a5c55ac61b54a86a3c3 (patch) | |
| tree | 9ca1c6e09858ebcefb0dc14f60c95293fb6976ef /scripts | |
| parent | 445881f6c8a28faae22a764c96449be86b48a96b (diff) | |
| download | binaryen-0faa68b9dfbe478c6d238a5c55ac61b54a86a3c3.tar.gz binaryen-0faa68b9dfbe478c6d238a5c55ac61b54a86a3c3.tar.bz2 binaryen-0faa68b9dfbe478c6d238a5c55ac61b54a86a3c3.zip | |
QFMA/QFMS instructions (#2328)
Renames the SIMDBitselect class to SIMDTernary and adds the new
{f32x4,f64x2}.qfm{a,s} ternary instructions. Because the SIMDBitselect
class is no more, this is a backwards-incompatible change to the C
interface. The new instructions are not yet used in the fuzzer because
they are not yet implemented in V8.
The corresponding LLVM commit is https://reviews.llvm.org/rL370556.
Diffstat (limited to 'scripts')
| -rwxr-xr-x | scripts/gen-s-parser.py | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/scripts/gen-s-parser.py b/scripts/gen-s-parser.py index 29f822f50..989634d9d 100755 --- a/scripts/gen-s-parser.py +++ b/scripts/gen-s-parser.py @@ -355,7 +355,7 @@ instructions = [ ("v128.and", "makeBinary(s, BinaryOp::AndVec128)"), ("v128.or", "makeBinary(s, BinaryOp::OrVec128)"), ("v128.xor", "makeBinary(s, BinaryOp::XorVec128)"), - ("v128.bitselect", "makeSIMDBitselect(s)"), + ("v128.bitselect", "makeSIMDTernary(s, SIMDTernaryOp::Bitselect)"), ("i8x16.neg", "makeUnary(s, UnaryOp::NegVecI8x16)"), ("i8x16.any_true", "makeUnary(s, UnaryOp::AnyTrueVecI8x16)"), ("i8x16.all_true", "makeUnary(s, UnaryOp::AllTrueVecI8x16)"), @@ -402,6 +402,8 @@ instructions = [ ("f32x4.abs", "makeUnary(s, UnaryOp::AbsVecF32x4)"), ("f32x4.neg", "makeUnary(s, UnaryOp::NegVecF32x4)"), ("f32x4.sqrt", "makeUnary(s, UnaryOp::SqrtVecF32x4)"), + ("f32x4.qfma", "makeSIMDTernary(s, SIMDTernaryOp::QFMAF32x4)"), + ("f32x4.qfms", "makeSIMDTernary(s, SIMDTernaryOp::QFMSF32x4)"), ("f32x4.add", "makeBinary(s, BinaryOp::AddVecF32x4)"), ("f32x4.sub", "makeBinary(s, BinaryOp::SubVecF32x4)"), ("f32x4.mul", "makeBinary(s, BinaryOp::MulVecF32x4)"), @@ -411,6 +413,8 @@ instructions = [ ("f64x2.abs", "makeUnary(s, UnaryOp::AbsVecF64x2)"), ("f64x2.neg", "makeUnary(s, UnaryOp::NegVecF64x2)"), ("f64x2.sqrt", "makeUnary(s, UnaryOp::SqrtVecF64x2)"), + ("f64x2.qfma", "makeSIMDTernary(s, SIMDTernaryOp::QFMAF64x2)"), + ("f64x2.qfms", "makeSIMDTernary(s, SIMDTernaryOp::QFMSF64x2)"), ("f64x2.add", "makeBinary(s, BinaryOp::AddVecF64x2)"), ("f64x2.sub", "makeBinary(s, BinaryOp::SubVecF64x2)"), ("f64x2.mul", "makeBinary(s, BinaryOp::MulVecF64x2)"), |