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| author | Brendan Dahl <brendan.dahl@gmail.com> | 2024-09-03 12:08:50 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-09-03 12:08:50 -0700 |
| commit | db9ee9434bd74ac8f1637ec109dc52e4b09794a7 (patch) | |
| tree | 3a6067d3467a74730ee92914444169f6ae48e29c /scripts | |
| parent | b7cdb8c2110dff5a9b096d766dac04cd8ec04cc9 (diff) | |
| download | binaryen-db9ee9434bd74ac8f1637ec109dc52e4b09794a7.tar.gz binaryen-db9ee9434bd74ac8f1637ec109dc52e4b09794a7.tar.bz2 binaryen-db9ee9434bd74ac8f1637ec109dc52e4b09794a7.zip | |
[FP16] Implement madd and nmadd. (#6878)
Specified at
https://github.com/WebAssembly/half-precision/blob/main/proposals/half-precision/Overview.md
A few notes:
- The F32x4 and F64x2 versions of madd and nmadd are missing spect
tests.
- For madd, the implementation was incorrectly doing `(b*c)+a` where it
should be `(a*b)+c`.
- For nmadd, the implementation was incorrectly doing `(-b*c)+a` where
it should be `-(a*b)+c`.
- There doesn't appear to be a great way to actually implement a fused
nmadd, but the spec allows the double rounded version I added.
Diffstat (limited to 'scripts')
| -rwxr-xr-x | scripts/gen-s-parser.py | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/scripts/gen-s-parser.py b/scripts/gen-s-parser.py index 0b5703b9e..9c39acb48 100755 --- a/scripts/gen-s-parser.py +++ b/scripts/gen-s-parser.py @@ -547,6 +547,8 @@ instructions = [ ("i32x4.relaxed_trunc_f32x4_u", "makeUnary(UnaryOp::RelaxedTruncUVecF32x4ToVecI32x4)"), ("i32x4.relaxed_trunc_f64x2_s_zero", "makeUnary(UnaryOp::RelaxedTruncZeroSVecF64x2ToVecI32x4)"), ("i32x4.relaxed_trunc_f64x2_u_zero", "makeUnary(UnaryOp::RelaxedTruncZeroUVecF64x2ToVecI32x4)"), + ("f16x8.relaxed_madd", "makeSIMDTernary(SIMDTernaryOp::RelaxedMaddVecF16x8)"), + ("f16x8.relaxed_nmadd", "makeSIMDTernary(SIMDTernaryOp::RelaxedNmaddVecF16x8)"), ("f32x4.relaxed_madd", "makeSIMDTernary(SIMDTernaryOp::RelaxedMaddVecF32x4)"), ("f32x4.relaxed_nmadd", "makeSIMDTernary(SIMDTernaryOp::RelaxedNmaddVecF32x4)"), ("f64x2.relaxed_madd", "makeSIMDTernary(SIMDTernaryOp::RelaxedMaddVecF64x2)"), |