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| author | Thomas Lively <7121787+tlively@users.noreply.github.com> | 2020-12-11 19:06:34 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-12-11 19:06:34 -0500 |
| commit | dd33ae0512aa97f537d40e61631d268c8a8fd17e (patch) | |
| tree | e5c219ba349e56940669bb873bb57a3f2626bf77 /src/ir/cost.h | |
| parent | 290147d8d43a7448d68939ec711b524ba4fb3fbd (diff) | |
| download | binaryen-dd33ae0512aa97f537d40e61631d268c8a8fd17e.tar.gz binaryen-dd33ae0512aa97f537d40e61631d268c8a8fd17e.tar.bz2 binaryen-dd33ae0512aa97f537d40e61631d268c8a8fd17e.zip | |
Prototype SIMD instructions implemented in LLVM (#3440)
- i64x2.eq (https://github.com/WebAssembly/simd/pull/381)
- i64x2 widens (https://github.com/WebAssembly/simd/pull/290)
- i64x2.bitmask (https://github.com/WebAssembly/simd/pull/368)
- signselect ops (https://github.com/WebAssembly/simd/pull/124)
Diffstat (limited to 'src/ir/cost.h')
| -rw-r--r-- | src/ir/cost.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/ir/cost.h b/src/ir/cost.h index 66a316bf6..c5b77ea01 100644 --- a/src/ir/cost.h +++ b/src/ir/cost.h @@ -191,6 +191,7 @@ struct CostAnalyzer : public OverriddenVisitor<CostAnalyzer, Index> { case NegVecI64x2: case AnyTrueVecI64x2: case AllTrueVecI64x2: + case BitmaskVecI64x2: case AbsVecF32x4: case NegVecF32x4: case SqrtVecF32x4: @@ -221,6 +222,10 @@ struct CostAnalyzer : public OverriddenVisitor<CostAnalyzer, Index> { case WidenHighSVecI16x8ToVecI32x4: case WidenLowUVecI16x8ToVecI32x4: case WidenHighUVecI16x8ToVecI32x4: + case WidenLowSVecI32x4ToVecI64x2: + case WidenHighSVecI32x4ToVecI64x2: + case WidenLowUVecI32x4ToVecI64x2: + case WidenHighUVecI32x4ToVecI64x2: ret = 1; break; case InvalidUnary: @@ -363,6 +368,7 @@ struct CostAnalyzer : public OverriddenVisitor<CostAnalyzer, Index> { case GtUVecI32x4: case GeSVecI32x4: case GeUVecI32x4: + case EqVecI64x2: case EqVecF32x4: case NeVecF32x4: case LtVecF32x4: @@ -508,6 +514,10 @@ struct CostAnalyzer : public OverriddenVisitor<CostAnalyzer, Index> { Index ret = 0; switch (curr->op) { case Bitselect: + case SignSelectVec8x16: + case SignSelectVec16x8: + case SignSelectVec32x4: + case SignSelectVec64x2: ret = 1; break; case QFMAF32x4: |