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| author | Thomas Lively <7121787+tlively@users.noreply.github.com> | 2021-04-05 12:33:25 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-04-05 12:33:25 -0700 |
| commit | 1bb172c789bb3a61aeaae78f5464d0544627ed3e (patch) | |
| tree | 6bcfd54944e52f9c3f8354a3d3f523f45a5ee670 /src/ir/features.h | |
| parent | c59df4cda843ef11ad261f5c889dddc9a9d59d3b (diff) | |
| download | binaryen-1bb172c789bb3a61aeaae78f5464d0544627ed3e.tar.gz binaryen-1bb172c789bb3a61aeaae78f5464d0544627ed3e.tar.bz2 binaryen-1bb172c789bb3a61aeaae78f5464d0544627ed3e.zip | |
Update SIMD names and opcodes (#3771)
Also removes experimental SIMD instructions that were not included in the final
spec proposal.
Diffstat (limited to 'src/ir/features.h')
| -rw-r--r-- | src/ir/features.h | 10 |
1 files changed, 1 insertions, 9 deletions
diff --git a/src/ir/features.h b/src/ir/features.h index aa87bd5bd..791a4dded 100644 --- a/src/ir/features.h +++ b/src/ir/features.h @@ -48,13 +48,10 @@ inline FeatureSet get(UnaryOp op) { case SplatVecF64x2: case NotVec128: case NegVecI8x16: - case AnyTrueVecI8x16: case AllTrueVecI8x16: case NegVecI16x8: - case AnyTrueVecI16x8: case AllTrueVecI16x8: case NegVecI32x4: - case AnyTrueVecI32x4: case AllTrueVecI32x4: case NegVecI64x2: case AbsVecF32x4: @@ -65,12 +62,8 @@ inline FeatureSet get(UnaryOp op) { case SqrtVecF64x2: case TruncSatSVecF32x4ToVecI32x4: case TruncSatUVecF32x4ToVecI32x4: - case TruncSatSVecF64x2ToVecI64x2: - case TruncSatUVecF64x2ToVecI64x2: case ConvertSVecI32x4ToVecF32x4: - case ConvertUVecI32x4ToVecF32x4: - case ConvertSVecI64x2ToVecF64x2: - case ConvertUVecI64x2ToVecF64x2: { + case ConvertUVecI32x4ToVecF32x4: { ret.setSIMD(); break; } @@ -141,7 +134,6 @@ inline FeatureSet get(BinaryOp op) { case SubVecI8x16: case SubSatSVecI8x16: case SubSatUVecI8x16: - case MulVecI8x16: case AddVecI16x8: case AddSatSVecI16x8: case AddSatUVecI16x8: |