diff options
author | Thomas Lively <7121787+tlively@users.noreply.github.com> | 2020-03-20 16:31:16 -0700 |
---|---|---|
committer | GitHub <noreply@github.com> | 2020-03-20 16:31:16 -0700 |
commit | 03ae7fcbfc5cedefd25c2414616cb1d3f77ab51b (patch) | |
tree | 17f6a9148ffd659f870dfe5745383fb1507e4d42 /src/js | |
parent | 39fda77da51f83b200fc63bbfbc4dd2ccbfc2388 (diff) | |
download | binaryen-03ae7fcbfc5cedefd25c2414616cb1d3f77ab51b.tar.gz binaryen-03ae7fcbfc5cedefd25c2414616cb1d3f77ab51b.tar.bz2 binaryen-03ae7fcbfc5cedefd25c2414616cb1d3f77ab51b.zip |
SIMD integer abs and bitmask instructions (#2703)
Adds full support for the {i8x16,i16x8,i32x4}.abs instructions merged
to the SIMD proposal in https://github.com/WebAssembly/simd/pull/128
as well as the {i8x16,i16x8,i32x4}.bitmask instructions proposed in
https://github.com/WebAssembly/simd/pull/201.
Diffstat (limited to 'src/js')
-rw-r--r-- | src/js/binaryen.js-post.js | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/src/js/binaryen.js-post.js b/src/js/binaryen.js-post.js index 39e23633b..49b02d336 100644 --- a/src/js/binaryen.js-post.js +++ b/src/js/binaryen.js-post.js @@ -344,9 +344,11 @@ function initializeConstants() { 'XorVec128', 'AndNotVec128', 'BitselectVec128', + 'AbsVecI8x16', 'NegVecI8x16', 'AnyTrueVecI8x16', 'AllTrueVecI8x16', + 'BitmaskVecI8x16', 'ShlVecI8x16', 'ShrSVecI8x16', 'ShrUVecI8x16', @@ -362,9 +364,11 @@ function initializeConstants() { 'MaxSVecI8x16', 'MaxUVecI8x16', 'AvgrUVecI8x16', + 'AbsVecI16x8', 'NegVecI16x8', 'AnyTrueVecI16x8', 'AllTrueVecI16x8', + 'BitmaskVecI16x8', 'ShlVecI16x8', 'ShrSVecI16x8', 'ShrUVecI16x8', @@ -381,9 +385,11 @@ function initializeConstants() { 'MaxUVecI16x8', 'AvgrUVecI16x8', 'DotSVecI16x8ToVecI32x4', + 'AbsVecI32x4', 'NegVecI32x4', 'AnyTrueVecI32x4', 'AllTrueVecI32x4', + 'BitmaskVecI32x4', 'ShlVecI32x4', 'ShrSVecI32x4', 'ShrUVecI32x4', @@ -1466,6 +1472,9 @@ function wrapModule(module, self) { 'ge_u': function(left, right) { return Module['_BinaryenBinary'](module, Module['GeUVecI8x16'], left, right); }, + 'abs': function(value) { + return Module['_BinaryenUnary'](module, Module['AbsVecI8x16'], value); + }, 'neg': function(value) { return Module['_BinaryenUnary'](module, Module['NegVecI8x16'], value); }, @@ -1475,6 +1484,9 @@ function wrapModule(module, self) { 'all_true': function(value) { return Module['_BinaryenUnary'](module, Module['AllTrueVecI8x16'], value); }, + 'bitmask': function(value) { + return Module['_BinaryenUnary'](module, Module['BitmaskVecI8x16'], value); + }, 'shl': function(vec, shift) { return Module['_BinaryenSIMDShift'](module, Module['ShlVecI8x16'], vec, shift); }, @@ -1571,6 +1583,9 @@ function wrapModule(module, self) { 'ge_u': function(left, right) { return Module['_BinaryenBinary'](module, Module['GeUVecI16x8'], left, right); }, + 'abs': function(value) { + return Module['_BinaryenUnary'](module, Module['AbsVecI16x8'], value); + }, 'neg': function(value) { return Module['_BinaryenUnary'](module, Module['NegVecI16x8'], value); }, @@ -1580,6 +1595,9 @@ function wrapModule(module, self) { 'all_true': function(value) { return Module['_BinaryenUnary'](module, Module['AllTrueVecI16x8'], value); }, + 'bitmask': function(value) { + return Module['_BinaryenUnary'](module, Module['BitmaskVecI16x8'], value); + }, 'shl': function(vec, shift) { return Module['_BinaryenSIMDShift'](module, Module['ShlVecI16x8'], vec, shift); }, @@ -1691,6 +1709,9 @@ function wrapModule(module, self) { 'ge_u': function(left, right) { return Module['_BinaryenBinary'](module, Module['GeUVecI32x4'], left, right); }, + 'abs': function(value) { + return Module['_BinaryenUnary'](module, Module['AbsVecI32x4'], value); + }, 'neg': function(value) { return Module['_BinaryenUnary'](module, Module['NegVecI32x4'], value); }, @@ -1700,6 +1721,9 @@ function wrapModule(module, self) { 'all_true': function(value) { return Module['_BinaryenUnary'](module, Module['AllTrueVecI32x4'], value); }, + 'bitmask': function(value) { + return Module['_BinaryenUnary'](module, Module['BitmaskVecI32x4'], value); + }, 'shl': function(vec, shift) { return Module['_BinaryenSIMDShift'](module, Module['ShlVecI32x4'], vec, shift); }, |