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| author | Brendan Dahl <brendan.dahl@gmail.com> | 2024-08-22 11:21:53 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-08-22 11:21:53 -0700 |
| commit | 95a280f70ef529c3c506d628648a96f2d267f4c1 (patch) | |
| tree | e77cf0b2337418fb7034c5c0e5b21de172b4bc30 /src/tools/fuzzing/fuzzing.cpp | |
| parent | 2d99e10c03e619b01688268319c1cd43f7539e33 (diff) | |
| download | binaryen-95a280f70ef529c3c506d628648a96f2d267f4c1.tar.gz binaryen-95a280f70ef529c3c506d628648a96f2d267f4c1.tar.bz2 binaryen-95a280f70ef529c3c506d628648a96f2d267f4c1.zip | |
[FP16] Add a feature flag for FP16. (#6864)
Ensure the "fp16" feature is enabled for FP16 instructions.
Diffstat (limited to 'src/tools/fuzzing/fuzzing.cpp')
| -rw-r--r-- | src/tools/fuzzing/fuzzing.cpp | 247 |
1 files changed, 130 insertions, 117 deletions
diff --git a/src/tools/fuzzing/fuzzing.cpp b/src/tools/fuzzing/fuzzing.cpp index a143d2ff2..7a3007e43 100644 --- a/src/tools/fuzzing/fuzzing.cpp +++ b/src/tools/fuzzing/fuzzing.cpp @@ -3271,116 +3271,119 @@ Expression* TranslateToFuzzReader::makeBinary(Type type) { } case Type::v128: { assert(wasm.features.hasSIMD()); - return buildBinary({pick(EqVecI8x16, - NeVecI8x16, - LtSVecI8x16, - LtUVecI8x16, - GtSVecI8x16, - GtUVecI8x16, - LeSVecI8x16, - LeUVecI8x16, - GeSVecI8x16, - GeUVecI8x16, - EqVecI16x8, - NeVecI16x8, - LtSVecI16x8, - LtUVecI16x8, - GtSVecI16x8, - GtUVecI16x8, - LeSVecI16x8, - LeUVecI16x8, - GeSVecI16x8, - GeUVecI16x8, - EqVecI32x4, - NeVecI32x4, - LtSVecI32x4, - LtUVecI32x4, - GtSVecI32x4, - GtUVecI32x4, - LeSVecI32x4, - LeUVecI32x4, - GeSVecI32x4, - GeUVecI32x4, - EqVecF16x8, - EqVecF16x8, - NeVecF16x8, - LtVecF16x8, - GtVecF16x8, - LeVecF16x8, - GeVecF16x8, - EqVecF32x4, - NeVecF32x4, - LtVecF32x4, - GtVecF32x4, - LeVecF32x4, - GeVecF32x4, - EqVecF64x2, - NeVecF64x2, - LtVecF64x2, - GtVecF64x2, - LeVecF64x2, - GeVecF64x2, - AndVec128, - OrVec128, - XorVec128, - AndNotVec128, - AddVecI8x16, - AddSatSVecI8x16, - AddSatUVecI8x16, - SubVecI8x16, - SubSatSVecI8x16, - SubSatUVecI8x16, - MinSVecI8x16, - MinUVecI8x16, - MaxSVecI8x16, - MaxUVecI8x16, - // TODO: avgr_u - // TODO: q15mulr_sat_s - // TODO: extmul - AddVecI16x8, - AddSatSVecI16x8, - AddSatUVecI16x8, - SubVecI16x8, - SubSatSVecI16x8, - SubSatUVecI16x8, - MulVecI16x8, - MinSVecI16x8, - MinUVecI16x8, - MaxSVecI16x8, - MaxUVecI16x8, - AddVecI32x4, - SubVecI32x4, - MulVecI32x4, - MinSVecI32x4, - MinUVecI32x4, - MaxSVecI32x4, - MaxUVecI32x4, - DotSVecI16x8ToVecI32x4, - AddVecI64x2, - SubVecI64x2, - AddVecF16x8, - SubVecF16x8, - MulVecF16x8, - DivVecF16x8, - MinVecF16x8, - MaxVecF16x8, - AddVecF32x4, - SubVecF32x4, - MulVecF32x4, - DivVecF32x4, - MinVecF32x4, - MaxVecF32x4, - AddVecF64x2, - SubVecF64x2, - MulVecF64x2, - DivVecF64x2, - MinVecF64x2, - MaxVecF64x2, - NarrowSVecI16x8ToVecI8x16, - NarrowUVecI16x8ToVecI8x16, - NarrowSVecI32x4ToVecI16x8, - NarrowUVecI32x4ToVecI16x8, - SwizzleVecI8x16), + return buildBinary({pick(FeatureOptions<BinaryOp>() + .add(FeatureSet::SIMD, + EqVecI8x16, + NeVecI8x16, + LtSVecI8x16, + LtUVecI8x16, + GtSVecI8x16, + GtUVecI8x16, + LeSVecI8x16, + LeUVecI8x16, + GeSVecI8x16, + GeUVecI8x16, + EqVecI16x8, + NeVecI16x8, + LtSVecI16x8, + LtUVecI16x8, + GtSVecI16x8, + GtUVecI16x8, + LeSVecI16x8, + LeUVecI16x8, + GeSVecI16x8, + GeUVecI16x8, + EqVecI32x4, + NeVecI32x4, + LtSVecI32x4, + LtUVecI32x4, + GtSVecI32x4, + GtUVecI32x4, + LeSVecI32x4, + LeUVecI32x4, + GeSVecI32x4, + GeUVecI32x4, + EqVecF32x4, + NeVecF32x4, + LtVecF32x4, + GtVecF32x4, + LeVecF32x4, + GeVecF32x4, + EqVecF64x2, + NeVecF64x2, + LtVecF64x2, + GtVecF64x2, + LeVecF64x2, + GeVecF64x2, + AndVec128, + OrVec128, + XorVec128, + AndNotVec128, + AddVecI8x16, + AddSatSVecI8x16, + AddSatUVecI8x16, + SubVecI8x16, + SubSatSVecI8x16, + SubSatUVecI8x16, + MinSVecI8x16, + MinUVecI8x16, + MaxSVecI8x16, + MaxUVecI8x16, + // TODO: avgr_u + // TODO: q15mulr_sat_s + // TODO: extmul + AddVecI16x8, + AddSatSVecI16x8, + AddSatUVecI16x8, + SubVecI16x8, + SubSatSVecI16x8, + SubSatUVecI16x8, + MulVecI16x8, + MinSVecI16x8, + MinUVecI16x8, + MaxSVecI16x8, + MaxUVecI16x8, + AddVecI32x4, + SubVecI32x4, + MulVecI32x4, + MinSVecI32x4, + MinUVecI32x4, + MaxSVecI32x4, + MaxUVecI32x4, + DotSVecI16x8ToVecI32x4, + AddVecI64x2, + SubVecI64x2, + AddVecF32x4, + SubVecF32x4, + MulVecF32x4, + DivVecF32x4, + MinVecF32x4, + MaxVecF32x4, + AddVecF64x2, + SubVecF64x2, + MulVecF64x2, + DivVecF64x2, + MinVecF64x2, + MaxVecF64x2, + NarrowSVecI16x8ToVecI8x16, + NarrowUVecI16x8ToVecI8x16, + NarrowSVecI32x4ToVecI16x8, + NarrowUVecI32x4ToVecI16x8, + SwizzleVecI8x16) + .add(FeatureSet::FP16, + EqVecF16x8, + EqVecF16x8, + NeVecF16x8, + LtVecF16x8, + GtVecF16x8, + LeVecF16x8, + GeVecF16x8, + AddVecF16x8, + SubVecF16x8, + MulVecF16x8, + DivVecF16x8, + MinVecF16x8, + MaxVecF16x8)), make(Type::v128), make(Type::v128)}); } @@ -3586,7 +3589,9 @@ Expression* TranslateToFuzzReader::makeSIMDExtract(Type type) { op = ExtractLaneVecI64x2; break; case Type::f32: - op = ExtractLaneVecF32x4; + op = pick(FeatureOptions<SIMDExtractOp>() + .add(FeatureSet::SIMD, ExtractLaneVecF32x4) + .add(FeatureSet::FP16, ExtractLaneVecF16x8)); break; case Type::f64: op = ExtractLaneVecF64x2; @@ -3621,12 +3626,16 @@ Expression* TranslateToFuzzReader::makeSIMDExtract(Type type) { } Expression* TranslateToFuzzReader::makeSIMDReplace() { - SIMDReplaceOp op = pick(ReplaceLaneVecI8x16, - ReplaceLaneVecI16x8, - ReplaceLaneVecI32x4, - ReplaceLaneVecI64x2, - ReplaceLaneVecF32x4, - ReplaceLaneVecF64x2); + SIMDReplaceOp op = + pick(FeatureOptions<SIMDReplaceOp>() + .add(FeatureSet::SIMD, + ReplaceLaneVecI8x16, + ReplaceLaneVecI16x8, + ReplaceLaneVecI32x4, + ReplaceLaneVecI64x2, + ReplaceLaneVecF32x4, + ReplaceLaneVecF64x2) + .add(FeatureSet::FeatureSet::FP16, ReplaceLaneVecF16x8)); Expression* vec = make(Type::v128); uint8_t index; Type lane_t; @@ -3647,6 +3656,10 @@ Expression* TranslateToFuzzReader::makeSIMDReplace() { index = upTo(2); lane_t = Type::i64; break; + case ReplaceLaneVecF16x8: + index = upTo(8); + lane_t = Type::f32; + break; case ReplaceLaneVecF32x4: index = upTo(4); lane_t = Type::f32; |