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author | Thomas Lively <7121787+tlively@users.noreply.github.com> | 2019-09-24 15:29:15 -0700 |
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committer | GitHub <noreply@github.com> | 2019-09-24 15:29:15 -0700 |
commit | 034ed383a968204427befda3f9fb8bb5d2f63f75 (patch) | |
tree | 36ae37db02cdae27416be250fe533d0f0bff77e8 /src/wasm-interpreter.h | |
parent | 835581f58eb5040656243f7345ebcacf6d7deee5 (diff) | |
download | binaryen-034ed383a968204427befda3f9fb8bb5d2f63f75.tar.gz binaryen-034ed383a968204427befda3f9fb8bb5d2f63f75.tar.bz2 binaryen-034ed383a968204427befda3f9fb8bb5d2f63f75.zip |
v128.andnot instruction (#2355)
As specified at https://github.com/WebAssembly/simd/pull/102.
Also fixes bugs in the JS API for other SIMD bitwise operators.
Diffstat (limited to 'src/wasm-interpreter.h')
-rw-r--r-- | src/wasm-interpreter.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/wasm-interpreter.h b/src/wasm-interpreter.h index a128cf6e5..94a3f0d54 100644 --- a/src/wasm-interpreter.h +++ b/src/wasm-interpreter.h @@ -740,6 +740,8 @@ public: return left.orV128(right); case XorVec128: return left.xorV128(right); + case AndNotVec128: + return left.andV128(right.notV128()); case AddVecI8x16: return left.addI8x16(right); |