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author | Thomas Lively <7121787+tlively@users.noreply.github.com> | 2019-11-01 18:22:05 -0700 |
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committer | GitHub <noreply@github.com> | 2019-11-01 18:22:05 -0700 |
commit | 0a5925a52cc0888fb61bc7b55c78666add5025cd (patch) | |
tree | d21ff1cc88829dcacbc33b4ddd23e2d467fd8cb1 /src/wasm-interpreter.h | |
parent | 90297e84007031ec884d829f973556d49c9b9467 (diff) | |
download | binaryen-0a5925a52cc0888fb61bc7b55c78666add5025cd.tar.gz binaryen-0a5925a52cc0888fb61bc7b55c78666add5025cd.tar.bz2 binaryen-0a5925a52cc0888fb61bc7b55c78666add5025cd.zip |
Add SIMD integer min and max instructions (#2416)
As proposed in https://github.com/WebAssembly/simd/pull/27.
Diffstat (limited to 'src/wasm-interpreter.h')
-rw-r--r-- | src/wasm-interpreter.h | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/src/wasm-interpreter.h b/src/wasm-interpreter.h index 5995808a5..f8cf3ae42 100644 --- a/src/wasm-interpreter.h +++ b/src/wasm-interpreter.h @@ -757,6 +757,14 @@ public: return left.subSaturateUI8x16(right); case MulVecI8x16: return left.mulI8x16(right); + case MinSVecI8x16: + return left.minSI8x16(right); + case MinUVecI8x16: + return left.minUI8x16(right); + case MaxSVecI8x16: + return left.maxSI8x16(right); + case MaxUVecI8x16: + return left.maxUI8x16(right); case AddVecI16x8: return left.addI16x8(right); case AddSatSVecI16x8: @@ -771,12 +779,28 @@ public: return left.subSaturateUI16x8(right); case MulVecI16x8: return left.mulI16x8(right); + case MinSVecI16x8: + return left.minSI16x8(right); + case MinUVecI16x8: + return left.minUI16x8(right); + case MaxSVecI16x8: + return left.maxSI16x8(right); + case MaxUVecI16x8: + return left.maxUI16x8(right); case AddVecI32x4: return left.addI32x4(right); case SubVecI32x4: return left.subI32x4(right); case MulVecI32x4: return left.mulI32x4(right); + case MinSVecI32x4: + return left.minSI32x4(right); + case MinUVecI32x4: + return left.minUI32x4(right); + case MaxSVecI32x4: + return left.maxSI32x4(right); + case MaxUVecI32x4: + return left.maxUI32x4(right); case AddVecI64x2: return left.addI64x2(right); case SubVecI64x2: |