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| author | Daniel Wirtz <dcode@dcode.io> | 2021-04-12 22:22:16 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-04-12 22:22:16 +0200 |
| commit | 0d7dac2923f9164ca7f1450b6f394ef8fa9d8a68 (patch) | |
| tree | b5ecd1defc11d31c77ea9ab9236282c5a85f9f0a /src/wasm-interpreter.h | |
| parent | 2e4c96fab93de97665648d4ae83164e177431ad8 (diff) | |
| download | binaryen-0d7dac2923f9164ca7f1450b6f394ef8fa9d8a68.tar.gz binaryen-0d7dac2923f9164ca7f1450b6f394ef8fa9d8a68.tar.bz2 binaryen-0d7dac2923f9164ca7f1450b6f394ef8fa9d8a68.zip | |
Rename SIMD extending load instructions (#3798)
Renames the SIMD instructions
* LoadExtSVec8x8ToVecI16x8 -> Load8x8SVec128
* LoadExtUVec8x8ToVecI16x8 -> Load8x8UVec128
* LoadExtSVec16x4ToVecI32x4 -> Load16x4SVec128
* LoadExtUVec16x4ToVecI32x4 -> Load16x4UVec128
* LoadExtSVec32x2ToVecI64x2 -> Load32x2SVec128
* LoadExtUVec32x2ToVecI64x2 -> Load32x2UVec128
Diffstat (limited to 'src/wasm-interpreter.h')
| -rw-r--r-- | src/wasm-interpreter.h | 36 |
1 files changed, 18 insertions, 18 deletions
diff --git a/src/wasm-interpreter.h b/src/wasm-interpreter.h index bb6361321..d76f3fabf 100644 --- a/src/wasm-interpreter.h +++ b/src/wasm-interpreter.h @@ -2686,12 +2686,12 @@ private: case Load32SplatVec128: case Load64SplatVec128: return visitSIMDLoadSplat(curr); - case LoadExtSVec8x8ToVecI16x8: - case LoadExtUVec8x8ToVecI16x8: - case LoadExtSVec16x4ToVecI32x4: - case LoadExtUVec16x4ToVecI32x4: - case LoadExtSVec32x2ToVecI64x2: - case LoadExtUVec32x2ToVecI64x2: + case Load8x8SVec128: + case Load8x8UVec128: + case Load16x4SVec128: + case Load16x4UVec128: + case Load32x2SVec128: + case Load32x2UVec128: return visitSIMDLoadExtend(curr); case Load32ZeroVec128: case Load64ZeroVec128: @@ -2742,17 +2742,17 @@ private: Address src(uint32_t(flow.getSingleValue().geti32())); auto loadLane = [&](Address addr) { switch (curr->op) { - case LoadExtSVec8x8ToVecI16x8: + case Load8x8SVec128: return Literal(int32_t(instance.externalInterface->load8s(addr))); - case LoadExtUVec8x8ToVecI16x8: + case Load8x8UVec128: return Literal(int32_t(instance.externalInterface->load8u(addr))); - case LoadExtSVec16x4ToVecI32x4: + case Load16x4SVec128: return Literal(int32_t(instance.externalInterface->load16s(addr))); - case LoadExtUVec16x4ToVecI32x4: + case Load16x4UVec128: return Literal(int32_t(instance.externalInterface->load16u(addr))); - case LoadExtSVec32x2ToVecI64x2: + case Load32x2SVec128: return Literal(int64_t(instance.externalInterface->load32s(addr))); - case LoadExtUVec32x2ToVecI64x2: + case Load32x2UVec128: return Literal(int64_t(instance.externalInterface->load32u(addr))); default: WASM_UNREACHABLE("unexpected op"); @@ -2768,18 +2768,18 @@ private: return Literal(lanes); }; switch (curr->op) { - case LoadExtSVec8x8ToVecI16x8: - case LoadExtUVec8x8ToVecI16x8: { + case Load8x8SVec128: + case Load8x8UVec128: { std::array<Literal, 8> lanes; return fillLanes(lanes, 1); } - case LoadExtSVec16x4ToVecI32x4: - case LoadExtUVec16x4ToVecI32x4: { + case Load16x4SVec128: + case Load16x4UVec128: { std::array<Literal, 4> lanes; return fillLanes(lanes, 2); } - case LoadExtSVec32x2ToVecI64x2: - case LoadExtUVec32x2ToVecI64x2: { + case Load32x2SVec128: + case Load32x2UVec128: { std::array<Literal, 2> lanes; return fillLanes(lanes, 4); } |