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| author | Daniel Wirtz <dcode@dcode.io> | 2021-04-11 19:58:43 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-04-11 19:58:43 +0200 |
| commit | 70d62322406b3eac5441efe1ebd7ba4058c4f4a7 (patch) | |
| tree | 45ee575c4d8fd7c58022f9c9e9aeb5cb72aa5f8d /src/wasm-interpreter.h | |
| parent | 67094a4a9b013a9705bcbf49ec7e0e8ab744389c (diff) | |
| download | binaryen-70d62322406b3eac5441efe1ebd7ba4058c4f4a7.tar.gz binaryen-70d62322406b3eac5441efe1ebd7ba4058c4f4a7.tar.bz2 binaryen-70d62322406b3eac5441efe1ebd7ba4058c4f4a7.zip | |
Rename various SIMD load instructions (#3795)
Renames the SIMD instructions
* LoadSplatVec8x16 -> Load8SplatVec128
* LoadSplatVec16x8 -> Load16SplatVec128
* LoadSplatVec32x4 -> Load32SplatVec128
* LoadSplatVec64x2 -> Load64SplatVec128
* Load32Zero -> Load32ZeroVec128
* Load64Zero -> Load64ZeroVec128
Diffstat (limited to 'src/wasm-interpreter.h')
| -rw-r--r-- | src/wasm-interpreter.h | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/src/wasm-interpreter.h b/src/wasm-interpreter.h index 2e464cdb4..bb6361321 100644 --- a/src/wasm-interpreter.h +++ b/src/wasm-interpreter.h @@ -2681,10 +2681,10 @@ private: Flow visitSIMDLoad(SIMDLoad* curr) { NOTE_ENTER("SIMDLoad"); switch (curr->op) { - case LoadSplatVec8x16: - case LoadSplatVec16x8: - case LoadSplatVec32x4: - case LoadSplatVec64x2: + case Load8SplatVec128: + case Load16SplatVec128: + case Load32SplatVec128: + case Load64SplatVec128: return visitSIMDLoadSplat(curr); case LoadExtSVec8x8ToVecI16x8: case LoadExtUVec8x8ToVecI16x8: @@ -2693,8 +2693,8 @@ private: case LoadExtSVec32x2ToVecI64x2: case LoadExtUVec32x2ToVecI64x2: return visitSIMDLoadExtend(curr); - case Load32Zero: - case Load64Zero: + case Load32ZeroVec128: + case Load64ZeroVec128: return visitSIMDLoadZero(curr); } WASM_UNREACHABLE("invalid op"); @@ -2710,16 +2710,16 @@ private: load.ptr = curr->ptr; Literal (Literal::*splat)() const = nullptr; switch (curr->op) { - case LoadSplatVec8x16: + case Load8SplatVec128: splat = &Literal::splatI8x16; break; - case LoadSplatVec16x8: + case Load16SplatVec128: splat = &Literal::splatI16x8; break; - case LoadSplatVec32x4: + case Load32SplatVec128: splat = &Literal::splatI32x4; break; - case LoadSplatVec64x2: + case Load64SplatVec128: load.type = Type::i64; splat = &Literal::splatI64x2; break; @@ -2797,8 +2797,8 @@ private: Address src = instance.getFinalAddress( curr, flow.getSingleValue(), curr->getMemBytes()); auto zero = - Literal::makeZero(curr->op == Load32Zero ? Type::i32 : Type::i64); - if (curr->op == Load32Zero) { + Literal::makeZero(curr->op == Load32ZeroVec128 ? Type::i32 : Type::i64); + if (curr->op == Load32ZeroVec128) { auto val = Literal(instance.externalInterface->load32u(src)); return Literal(std::array<Literal, 4>{{val, zero, zero, zero}}); } else { |