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authorThomas Lively <7121787+tlively@users.noreply.github.com>2021-01-05 19:27:53 -0500
committerGitHub <noreply@github.com>2021-01-05 16:27:53 -0800
commitb79661ee03fc74b3f860bf04e6f1019f7b11c722 (patch)
tree5f25958499f95e219fadc8d4cc2e2b0801bddf6b /src/wasm-interpreter.h
parent3e5ce644e0336bc7ce82a5f6df6b1f671097556d (diff)
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Prototype SIMD extending pairwise add instructions (#3466)
As proposed in https://github.com/WebAssembly/simd/pull/380, using the opcodes used in LLVM and V8. Since these opcodes overlap with the opcodes of i64x2.all_true and i64x2.any_true, which have long since been removed from the SIMD proposal, this PR also removes those instructions.
Diffstat (limited to 'src/wasm-interpreter.h')
-rw-r--r--src/wasm-interpreter.h12
1 files changed, 8 insertions, 4 deletions
diff --git a/src/wasm-interpreter.h b/src/wasm-interpreter.h
index 019a56db1..3d963269d 100644
--- a/src/wasm-interpreter.h
+++ b/src/wasm-interpreter.h
@@ -488,10 +488,6 @@ public:
return value.bitmaskI32x4();
case NegVecI64x2:
return value.negI64x2();
- case AnyTrueVecI64x2:
- return value.anyTrueI64x2();
- case AllTrueVecI64x2:
- return value.allTrueI64x2();
case BitmaskVecI64x2:
WASM_UNREACHABLE("unimp");
case AbsVecF32x4:
@@ -522,6 +518,14 @@ public:
return value.truncF64x2();
case NearestVecF64x2:
return value.nearestF64x2();
+ case ExtAddPairwiseSVecI8x16ToI16x8:
+ WASM_UNREACHABLE("unimp");
+ case ExtAddPairwiseUVecI8x16ToI16x8:
+ WASM_UNREACHABLE("unimp");
+ case ExtAddPairwiseSVecI16x8ToI32x4:
+ WASM_UNREACHABLE("unimp");
+ case ExtAddPairwiseUVecI16x8ToI32x4:
+ WASM_UNREACHABLE("unimp");
case TruncSatSVecF32x4ToVecI32x4:
return value.truncSatToSI32x4();
case TruncSatUVecF32x4ToVecI32x4: