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| author | Daniel Wirtz <dcode@dcode.io> | 2021-04-12 22:22:16 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-04-12 22:22:16 +0200 |
| commit | 0d7dac2923f9164ca7f1450b6f394ef8fa9d8a68 (patch) | |
| tree | b5ecd1defc11d31c77ea9ab9236282c5a85f9f0a /src/wasm/wasm-binary.cpp | |
| parent | 2e4c96fab93de97665648d4ae83164e177431ad8 (diff) | |
| download | binaryen-0d7dac2923f9164ca7f1450b6f394ef8fa9d8a68.tar.gz binaryen-0d7dac2923f9164ca7f1450b6f394ef8fa9d8a68.tar.bz2 binaryen-0d7dac2923f9164ca7f1450b6f394ef8fa9d8a68.zip | |
Rename SIMD extending load instructions (#3798)
Renames the SIMD instructions
* LoadExtSVec8x8ToVecI16x8 -> Load8x8SVec128
* LoadExtUVec8x8ToVecI16x8 -> Load8x8UVec128
* LoadExtSVec16x4ToVecI32x4 -> Load16x4SVec128
* LoadExtUVec16x4ToVecI32x4 -> Load16x4UVec128
* LoadExtSVec32x2ToVecI64x2 -> Load32x2SVec128
* LoadExtUVec32x2ToVecI64x2 -> Load32x2UVec128
Diffstat (limited to 'src/wasm/wasm-binary.cpp')
| -rw-r--r-- | src/wasm/wasm-binary.cpp | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/wasm/wasm-binary.cpp b/src/wasm/wasm-binary.cpp index 4ca434bdf..b7a04a324 100644 --- a/src/wasm/wasm-binary.cpp +++ b/src/wasm/wasm-binary.cpp @@ -5850,27 +5850,27 @@ bool WasmBinaryBuilder::maybeVisitSIMDLoad(Expression*& out, uint32_t code) { break; case BinaryConsts::V128Load8x8S: curr = allocator.alloc<SIMDLoad>(); - curr->op = LoadExtSVec8x8ToVecI16x8; + curr->op = Load8x8SVec128; break; case BinaryConsts::V128Load8x8U: curr = allocator.alloc<SIMDLoad>(); - curr->op = LoadExtUVec8x8ToVecI16x8; + curr->op = Load8x8UVec128; break; case BinaryConsts::V128Load16x4S: curr = allocator.alloc<SIMDLoad>(); - curr->op = LoadExtSVec16x4ToVecI32x4; + curr->op = Load16x4SVec128; break; case BinaryConsts::V128Load16x4U: curr = allocator.alloc<SIMDLoad>(); - curr->op = LoadExtUVec16x4ToVecI32x4; + curr->op = Load16x4UVec128; break; case BinaryConsts::V128Load32x2S: curr = allocator.alloc<SIMDLoad>(); - curr->op = LoadExtSVec32x2ToVecI64x2; + curr->op = Load32x2SVec128; break; case BinaryConsts::V128Load32x2U: curr = allocator.alloc<SIMDLoad>(); - curr->op = LoadExtUVec32x2ToVecI64x2; + curr->op = Load32x2UVec128; break; case BinaryConsts::V128Load32Zero: curr = allocator.alloc<SIMDLoad>(); |