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author | Thomas Lively <7121787+tlively@users.noreply.github.com> | 2020-10-22 21:47:17 -0700 |
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committer | GitHub <noreply@github.com> | 2020-10-22 21:47:17 -0700 |
commit | daf0782b7754e225c9063f9fbf5195b4b4a3c7e3 (patch) | |
tree | d0004ebe92a2559e8bfcd86c4bdfdf972dc81432 /src/wasm/wasm.cpp | |
parent | a2fa37eb94fdd6896f4d90f22e34fbd5f028d742 (diff) | |
download | binaryen-daf0782b7754e225c9063f9fbf5195b4b4a3c7e3.tar.gz binaryen-daf0782b7754e225c9063f9fbf5195b4b4a3c7e3.tar.bz2 binaryen-daf0782b7754e225c9063f9fbf5195b4b4a3c7e3.zip |
Implement v128.{load,store}{8,16,32,64}_lane instructions (#3278)
These instructions are proposed in https://github.com/WebAssembly/simd/pull/350.
This PR implements them throughout Binaryen except in the C/JS APIs and in the
fuzzer, where it leaves TODOs instead. Right now these instructions are just
being implemented for prototyping so adding them to the APIs isn't critical and
they aren't generally available to be fuzzed in Wasm engines.
Diffstat (limited to 'src/wasm/wasm.cpp')
-rw-r--r-- | src/wasm/wasm.cpp | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/src/wasm/wasm.cpp b/src/wasm/wasm.cpp index 2052afa89..472902ad5 100644 --- a/src/wasm/wasm.cpp +++ b/src/wasm/wasm.cpp @@ -175,6 +175,8 @@ const char* getExpressionName(Expression* curr) { return "simd_shift"; case Expression::Id::SIMDLoadId: return "simd_load"; + case Expression::Id::SIMDLoadStoreLaneId: + return "simd_load_store_lane"; case Expression::Id::MemoryInitId: return "memory_init"; case Expression::Id::DataDropId: @@ -674,6 +676,48 @@ Index SIMDLoad::getMemBytes() { WASM_UNREACHABLE("unexpected op"); } +void SIMDLoadStoreLane::finalize() { + assert(ptr && vec); + type = isLoad() ? Type::v128 : Type::none; + if (ptr->type == Type::unreachable || vec->type == Type::unreachable) { + type = Type::unreachable; + } +} + +Index SIMDLoadStoreLane::getMemBytes() { + switch (op) { + case LoadLaneVec8x16: + case StoreLaneVec8x16: + return 1; + case LoadLaneVec16x8: + case StoreLaneVec16x8: + return 2; + case LoadLaneVec32x4: + case StoreLaneVec32x4: + return 4; + case LoadLaneVec64x2: + case StoreLaneVec64x2: + return 8; + } + WASM_UNREACHABLE("unexpected op"); +} + +bool SIMDLoadStoreLane::isStore() { + switch (op) { + case StoreLaneVec8x16: + case StoreLaneVec16x8: + case StoreLaneVec32x4: + case StoreLaneVec64x2: + return true; + case LoadLaneVec16x8: + case LoadLaneVec32x4: + case LoadLaneVec64x2: + case LoadLaneVec8x16: + return false; + } + WASM_UNREACHABLE("unexpected op"); +} + Const* Const::set(Literal value_) { value = value_; type = value.type; |