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authorBrendan Dahl <brendan.dahl@gmail.com>2024-08-09 09:13:33 -0700
committerGitHub <noreply@github.com>2024-08-09 09:13:33 -0700
commitb3e22d29451fbf52521d59ea34e8a5d735c4149c (patch)
tree034a8d510b7d6fa7589115ac2a046b11585390ce /src
parentd945aa489a1ad62c130e04ceea8492c7a728ab57 (diff)
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[FP16] Implement relation operations. (#6825)
Specified at https://github.com/WebAssembly/half-precision/blob/main/proposals/half-precision/Overview.md
Diffstat (limited to 'src')
-rw-r--r--src/gen-s-parser.inc57
-rw-r--r--src/ir/child-typer.h6
-rw-r--r--src/ir/cost.h6
-rw-r--r--src/literal.h6
-rw-r--r--src/passes/Print.cpp18
-rw-r--r--src/tools/fuzzing/fuzzing.cpp7
-rw-r--r--src/wasm-binary.h6
-rw-r--r--src/wasm-interpreter.h12
-rw-r--r--src/wasm.h6
-rw-r--r--src/wasm/literal.cpp18
-rw-r--r--src/wasm/wasm-binary.cpp24
-rw-r--r--src/wasm/wasm-stack.cpp18
-rw-r--r--src/wasm/wasm-validator.cpp6
13 files changed, 187 insertions, 3 deletions
diff --git a/src/gen-s-parser.inc b/src/gen-s-parser.inc
index 33cddcb26..d6eaf851d 100644
--- a/src/gen-s-parser.inc
+++ b/src/gen-s-parser.inc
@@ -309,9 +309,60 @@ switch (buf[0]) {
switch (buf[1]) {
case '1': {
switch (buf[6]) {
- case 'e':
- if (op == "f16x8.extract_lane"sv) {
- CHECK_ERR(makeSIMDExtract(ctx, pos, annotations, SIMDExtractOp::ExtractLaneVecF16x8, 8));
+ case 'e': {
+ switch (buf[7]) {
+ case 'q':
+ if (op == "f16x8.eq"sv) {
+ CHECK_ERR(makeBinary(ctx, pos, annotations, BinaryOp::EqVecF16x8));
+ return Ok{};
+ }
+ goto parse_error;
+ case 'x':
+ if (op == "f16x8.extract_lane"sv) {
+ CHECK_ERR(makeSIMDExtract(ctx, pos, annotations, SIMDExtractOp::ExtractLaneVecF16x8, 8));
+ return Ok{};
+ }
+ goto parse_error;
+ default: goto parse_error;
+ }
+ }
+ case 'g': {
+ switch (buf[7]) {
+ case 'e':
+ if (op == "f16x8.ge"sv) {
+ CHECK_ERR(makeBinary(ctx, pos, annotations, BinaryOp::GeVecF16x8));
+ return Ok{};
+ }
+ goto parse_error;
+ case 't':
+ if (op == "f16x8.gt"sv) {
+ CHECK_ERR(makeBinary(ctx, pos, annotations, BinaryOp::GtVecF16x8));
+ return Ok{};
+ }
+ goto parse_error;
+ default: goto parse_error;
+ }
+ }
+ case 'l': {
+ switch (buf[7]) {
+ case 'e':
+ if (op == "f16x8.le"sv) {
+ CHECK_ERR(makeBinary(ctx, pos, annotations, BinaryOp::LeVecF16x8));
+ return Ok{};
+ }
+ goto parse_error;
+ case 't':
+ if (op == "f16x8.lt"sv) {
+ CHECK_ERR(makeBinary(ctx, pos, annotations, BinaryOp::LtVecF16x8));
+ return Ok{};
+ }
+ goto parse_error;
+ default: goto parse_error;
+ }
+ }
+ case 'n':
+ if (op == "f16x8.ne"sv) {
+ CHECK_ERR(makeBinary(ctx, pos, annotations, BinaryOp::NeVecF16x8));
return Ok{};
}
goto parse_error;
diff --git a/src/ir/child-typer.h b/src/ir/child-typer.h
index 17717a32c..2bfaefaff 100644
--- a/src/ir/child-typer.h
+++ b/src/ir/child-typer.h
@@ -558,6 +558,12 @@ template<typename Subtype> struct ChildTyper : OverriddenVisitor<Subtype> {
case LeSVecI64x2:
case GtSVecI64x2:
case GeSVecI64x2:
+ case EqVecF16x8:
+ case NeVecF16x8:
+ case LtVecF16x8:
+ case LeVecF16x8:
+ case GtVecF16x8:
+ case GeVecF16x8:
case EqVecF32x4:
case NeVecF32x4:
case LtVecF32x4:
diff --git a/src/ir/cost.h b/src/ir/cost.h
index 06512d656..ab8ae90ae 100644
--- a/src/ir/cost.h
+++ b/src/ir/cost.h
@@ -398,6 +398,12 @@ struct CostAnalyzer : public OverriddenVisitor<CostAnalyzer, CostType> {
case LeSVecI64x2:
case GtSVecI64x2:
case GeSVecI64x2:
+ case EqVecF16x8:
+ case NeVecF16x8:
+ case LtVecF16x8:
+ case LeVecF16x8:
+ case GtVecF16x8:
+ case GeVecF16x8:
case EqVecF32x4:
case NeVecF32x4:
case LtVecF32x4:
diff --git a/src/literal.h b/src/literal.h
index 63bbf6e74..d247b0c84 100644
--- a/src/literal.h
+++ b/src/literal.h
@@ -509,6 +509,12 @@ public:
Literal gtSI64x2(const Literal& other) const;
Literal leSI64x2(const Literal& other) const;
Literal geSI64x2(const Literal& other) const;
+ Literal eqF16x8(const Literal& other) const;
+ Literal neF16x8(const Literal& other) const;
+ Literal ltF16x8(const Literal& other) const;
+ Literal gtF16x8(const Literal& other) const;
+ Literal leF16x8(const Literal& other) const;
+ Literal geF16x8(const Literal& other) const;
Literal eqF32x4(const Literal& other) const;
Literal neF32x4(const Literal& other) const;
Literal ltF32x4(const Literal& other) const;
diff --git a/src/passes/Print.cpp b/src/passes/Print.cpp
index fd22f1b71..5c83e89f1 100644
--- a/src/passes/Print.cpp
+++ b/src/passes/Print.cpp
@@ -1689,6 +1689,24 @@ struct PrintExpressionContents
case GeSVecI64x2:
o << "i64x2.ge_s";
break;
+ case EqVecF16x8:
+ o << "f16x8.eq";
+ break;
+ case NeVecF16x8:
+ o << "f16x8.ne";
+ break;
+ case LtVecF16x8:
+ o << "f16x8.lt";
+ break;
+ case GtVecF16x8:
+ o << "f16x8.gt";
+ break;
+ case LeVecF16x8:
+ o << "f16x8.le";
+ break;
+ case GeVecF16x8:
+ o << "f16x8.ge";
+ break;
case EqVecF32x4:
o << "f32x4.eq";
break;
diff --git a/src/tools/fuzzing/fuzzing.cpp b/src/tools/fuzzing/fuzzing.cpp
index fd0dfb26c..64780696b 100644
--- a/src/tools/fuzzing/fuzzing.cpp
+++ b/src/tools/fuzzing/fuzzing.cpp
@@ -3288,6 +3288,13 @@ Expression* TranslateToFuzzReader::makeBinary(Type type) {
LeUVecI32x4,
GeSVecI32x4,
GeUVecI32x4,
+ EqVecF16x8,
+ EqVecF16x8,
+ NeVecF16x8,
+ LtVecF16x8,
+ GtVecF16x8,
+ LeVecF16x8,
+ GeVecF16x8,
EqVecF32x4,
NeVecF32x4,
LtVecF32x4,
diff --git a/src/wasm-binary.h b/src/wasm-binary.h
index 38bf5d475..d568abd6c 100644
--- a/src/wasm-binary.h
+++ b/src/wasm-binary.h
@@ -1057,6 +1057,12 @@ enum ASTNodes {
F16x8Splat = 0x120,
F16x8ExtractLane = 0x121,
F16x8ReplaceLane = 0x122,
+ F16x8Eq = 0x137,
+ F16x8Ne = 0x138,
+ F16x8Lt = 0x139,
+ F16x8Gt = 0x13a,
+ F16x8Le = 0x13b,
+ F16x8Ge = 0x13c,
// bulk memory opcodes
diff --git a/src/wasm-interpreter.h b/src/wasm-interpreter.h
index f59a005b6..7fd5b3cd3 100644
--- a/src/wasm-interpreter.h
+++ b/src/wasm-interpreter.h
@@ -864,6 +864,18 @@ public:
return left.leSI64x2(right);
case GeSVecI64x2:
return left.geSI64x2(right);
+ case EqVecF16x8:
+ return left.eqF16x8(right);
+ case NeVecF16x8:
+ return left.neF16x8(right);
+ case LtVecF16x8:
+ return left.ltF16x8(right);
+ case GtVecF16x8:
+ return left.gtF16x8(right);
+ case LeVecF16x8:
+ return left.leF16x8(right);
+ case GeVecF16x8:
+ return left.geF16x8(right);
case EqVecF32x4:
return left.eqF32x4(right);
case NeVecF32x4:
diff --git a/src/wasm.h b/src/wasm.h
index 56e94fef7..e47b7c6ed 100644
--- a/src/wasm.h
+++ b/src/wasm.h
@@ -381,6 +381,12 @@ enum BinaryOp {
GtSVecI64x2,
LeSVecI64x2,
GeSVecI64x2,
+ EqVecF16x8,
+ NeVecF16x8,
+ LtVecF16x8,
+ GtVecF16x8,
+ LeVecF16x8,
+ GeVecF16x8,
EqVecF32x4,
NeVecF32x4,
LtVecF32x4,
diff --git a/src/wasm/literal.cpp b/src/wasm/literal.cpp
index a532b92d0..b0dcf5177 100644
--- a/src/wasm/literal.cpp
+++ b/src/wasm/literal.cpp
@@ -2209,6 +2209,24 @@ Literal Literal::geSI64x2(const Literal& other) const {
return compare<2, &Literal::getLanesI64x2, &Literal::geS, int64_t>(*this,
other);
}
+Literal Literal::eqF16x8(const Literal& other) const {
+ return compare<8, &Literal::getLanesF16x8, &Literal::eq>(*this, other);
+}
+Literal Literal::neF16x8(const Literal& other) const {
+ return compare<8, &Literal::getLanesF16x8, &Literal::ne>(*this, other);
+}
+Literal Literal::ltF16x8(const Literal& other) const {
+ return compare<8, &Literal::getLanesF16x8, &Literal::lt>(*this, other);
+}
+Literal Literal::gtF16x8(const Literal& other) const {
+ return compare<8, &Literal::getLanesF16x8, &Literal::gt>(*this, other);
+}
+Literal Literal::leF16x8(const Literal& other) const {
+ return compare<8, &Literal::getLanesF16x8, &Literal::le>(*this, other);
+}
+Literal Literal::geF16x8(const Literal& other) const {
+ return compare<8, &Literal::getLanesF16x8, &Literal::ge>(*this, other);
+}
Literal Literal::eqF32x4(const Literal& other) const {
return compare<4, &Literal::getLanesF32x4, &Literal::eq>(*this, other);
}
diff --git a/src/wasm/wasm-binary.cpp b/src/wasm/wasm-binary.cpp
index 5eaa84515..d9985212f 100644
--- a/src/wasm/wasm-binary.cpp
+++ b/src/wasm/wasm-binary.cpp
@@ -5846,6 +5846,30 @@ bool WasmBinaryReader::maybeVisitSIMDBinary(Expression*& out, uint32_t code) {
curr = allocator.alloc<Binary>();
curr->op = GeSVecI64x2;
break;
+ case BinaryConsts::F16x8Eq:
+ curr = allocator.alloc<Binary>();
+ curr->op = EqVecF16x8;
+ break;
+ case BinaryConsts::F16x8Ne:
+ curr = allocator.alloc<Binary>();
+ curr->op = NeVecF16x8;
+ break;
+ case BinaryConsts::F16x8Lt:
+ curr = allocator.alloc<Binary>();
+ curr->op = LtVecF16x8;
+ break;
+ case BinaryConsts::F16x8Gt:
+ curr = allocator.alloc<Binary>();
+ curr->op = GtVecF16x8;
+ break;
+ case BinaryConsts::F16x8Le:
+ curr = allocator.alloc<Binary>();
+ curr->op = LeVecF16x8;
+ break;
+ case BinaryConsts::F16x8Ge:
+ curr = allocator.alloc<Binary>();
+ curr->op = GeVecF16x8;
+ break;
case BinaryConsts::F32x4Eq:
curr = allocator.alloc<Binary>();
curr->op = EqVecF32x4;
diff --git a/src/wasm/wasm-stack.cpp b/src/wasm/wasm-stack.cpp
index 19b98769b..a9b582f43 100644
--- a/src/wasm/wasm-stack.cpp
+++ b/src/wasm/wasm-stack.cpp
@@ -1643,6 +1643,24 @@ void BinaryInstWriter::visitBinary(Binary* curr) {
case GeSVecI64x2:
o << int8_t(BinaryConsts::SIMDPrefix) << U32LEB(BinaryConsts::I64x2GeS);
break;
+ case EqVecF16x8:
+ o << int8_t(BinaryConsts::SIMDPrefix) << U32LEB(BinaryConsts::F16x8Eq);
+ break;
+ case NeVecF16x8:
+ o << int8_t(BinaryConsts::SIMDPrefix) << U32LEB(BinaryConsts::F16x8Ne);
+ break;
+ case LtVecF16x8:
+ o << int8_t(BinaryConsts::SIMDPrefix) << U32LEB(BinaryConsts::F16x8Lt);
+ break;
+ case GtVecF16x8:
+ o << int8_t(BinaryConsts::SIMDPrefix) << U32LEB(BinaryConsts::F16x8Gt);
+ break;
+ case LeVecF16x8:
+ o << int8_t(BinaryConsts::SIMDPrefix) << U32LEB(BinaryConsts::F16x8Le);
+ break;
+ case GeVecF16x8:
+ o << int8_t(BinaryConsts::SIMDPrefix) << U32LEB(BinaryConsts::F16x8Ge);
+ break;
case EqVecF32x4:
o << int8_t(BinaryConsts::SIMDPrefix) << U32LEB(BinaryConsts::F32x4Eq);
break;
diff --git a/src/wasm/wasm-validator.cpp b/src/wasm/wasm-validator.cpp
index 6e59ce8d8..b35d1b3be 100644
--- a/src/wasm/wasm-validator.cpp
+++ b/src/wasm/wasm-validator.cpp
@@ -1743,6 +1743,12 @@ void FunctionValidator::visitBinary(Binary* curr) {
case LeSVecI64x2:
case GtSVecI64x2:
case GeSVecI64x2:
+ case EqVecF16x8:
+ case NeVecF16x8:
+ case LtVecF16x8:
+ case LeVecF16x8:
+ case GtVecF16x8:
+ case GeVecF16x8:
case EqVecF32x4:
case NeVecF32x4:
case LtVecF32x4: