Update relaxed SIMD instructions

Update the opcodes for all relaxed SIMD instructions and remove the unsigned dot
product instructions that are no longer in the proposal.

9 files changed, 42 insertions, 88 deletions

diff --git a/src/gen-s-parser.inc b/src/gen-s-parser.inc
index 411196986..baeab95ec 100644
--- a/src/gen-s-parser.inc
+++ b/src/gen-s-parser.inc
@@ -933,17 +933,9 @@ switch (op[0]) {
           case 'b':
             if (strcmp(op, "i16x8.bitmask") == 0) { return makeUnary(s, UnaryOp::BitmaskVecI16x8); }
             goto parse_error;
-          case 'd': {
-            switch (op[22]) {
-              case 's':
-                if (strcmp(op, "i16x8.dot_i8x16_i7x16_s") == 0) { return makeBinary(s, BinaryOp::DotI8x16I7x16SToVecI16x8); }
-                goto parse_error;
-              case 'u':
-                if (strcmp(op, "i16x8.dot_i8x16_i7x16_u") == 0) { return makeBinary(s, BinaryOp::DotI8x16I7x16UToVecI16x8); }
-                goto parse_error;
-              default: goto parse_error;
-            }
-          }
+          case 'd':
+            if (strcmp(op, "i16x8.dot_i8x16_i7x16_s") == 0) { return makeBinary(s, BinaryOp::DotI8x16I7x16SToVecI16x8); }
+            goto parse_error;
           case 'e': {
             switch (op[7]) {
               case 'q':
@@ -1708,17 +1700,9 @@ switch (op[0]) {
                       case '1':
                         if (strcmp(op, "i32x4.dot_i16x8_s") == 0) { return makeBinary(s, BinaryOp::DotSVecI16x8ToVecI32x4); }
                         goto parse_error;
-                      case '8': {
-                        switch (op[26]) {
-                          case 's':
-                            if (strcmp(op, "i32x4.dot_i8x16_i7x16_add_s") == 0) { return makeSIMDTernary(s, SIMDTernaryOp::DotI8x16I7x16AddSToVecI32x4); }
-                            goto parse_error;
-                          case 'u':
-                            if (strcmp(op, "i32x4.dot_i8x16_i7x16_add_u") == 0) { return makeSIMDTernary(s, SIMDTernaryOp::DotI8x16I7x16AddUToVecI32x4); }
-                            goto parse_error;
-                          default: goto parse_error;
-                        }
-                      }
+                      case '8':
+                        if (strcmp(op, "i32x4.dot_i8x16_i7x16_add_s") == 0) { return makeSIMDTernary(s, SIMDTernaryOp::DotI8x16I7x16AddSToVecI32x4); }
+                        goto parse_error;
                       default: goto parse_error;
                     }
                   }
diff --git a/src/ir/cost.h b/src/ir/cost.h
index 276c3303f..8502a7610 100644
--- a/src/ir/cost.h
+++ b/src/ir/cost.h
@@ -501,7 +501,6 @@ struct CostAnalyzer : public OverriddenVisitor<CostAnalyzer, CostType> {
       case RelaxedSwizzleVecI8x16:
       case RelaxedQ15MulrSVecI16x8:
       case DotI8x16I7x16SToVecI16x8:
-      case DotI8x16I7x16UToVecI16x8:
         ret = 1;
         break;
       case InvalidBinary:
@@ -550,7 +549,6 @@ struct CostAnalyzer : public OverriddenVisitor<CostAnalyzer, CostType> {
       case RelaxedFmaVecF64x2:
       case RelaxedFmsVecF64x2:
       case DotI8x16I7x16AddSToVecI32x4:
-      case DotI8x16I7x16AddUToVecI32x4:
         ret = 1;
         break;
     }
diff --git a/src/passes/Print.cpp b/src/passes/Print.cpp
index 3f22265eb..a87b2e643 100644
--- a/src/passes/Print.cpp
+++ b/src/passes/Print.cpp
@@ -686,9 +686,6 @@ struct PrintExpressionContents
       case DotI8x16I7x16AddSToVecI32x4:
         o << "i32x4.dot_i8x16_i7x16_add_s";
         break;
-      case DotI8x16I7x16AddUToVecI32x4:
-        o << "i32x4.dot_i8x16_i7x16_add_u";
-        break;
     }
     restoreNormalColor(o);
   }
@@ -1863,9 +1860,6 @@ struct PrintExpressionContents
       case DotI8x16I7x16SToVecI16x8:
         o << "i16x8.dot_i8x16_i7x16_s";
         break;
-      case DotI8x16I7x16UToVecI16x8:
-        o << "i16x8.dot_i8x16_i7x16_u";
-        break;
 
       case InvalidBinary:
         WASM_UNREACHABLE("unvalid binary operator");
diff --git a/src/wasm-binary.h b/src/wasm-binary.h
index 58dcd2224..96927b10e 100644
--- a/src/wasm-binary.h
+++ b/src/wasm-binary.h
@@ -919,11 +919,11 @@ enum ASTNodes {
 
   I32x4Abs = 0xa0,
   I32x4Neg = 0xa1,
-  // 0xa2 for relaxed SIMD
+  // 0xa2 unused
   I32x4AllTrue = 0xa3,
   I32x4Bitmask = 0xa4,
-  // 0xa5 for relaxed SIMD
-  // 0xa6 for relaxed SIMD
+  // 0xa5 unused
+  // 0xa6 unused
   I32x4ExtendLowI16x8S = 0xa7,
   I32x4ExtendHighI16x8S = 0xa8,
   I32x4ExtendLowI16x8U = 0xa9,
@@ -932,12 +932,12 @@ enum ASTNodes {
   I32x4ShrS = 0xac,
   I32x4ShrU = 0xad,
   I32x4Add = 0xae,
-  // 0xaf for relaxed SIMD
-  // 0xb0 for relaxed SIMD
+  // 0xaf unused
+  // 0xb0 unused
   I32x4Sub = 0xb1,
-  // 0xb2 for relaxed SIMD
-  // 0xb3 for relaxed SIMD
-  // 0xb4 for relaxed SIMD
+  // 0xb2 unused
+  // 0xb3 unused
+  // 0xb4 unused
   I32x4Mul = 0xb5,
   I32x4MinS = 0xb6,
   I32x4MinU = 0xb7,
@@ -955,8 +955,8 @@ enum ASTNodes {
   // 0xc2 unused
   I64x2AllTrue = 0xc3,
   I64x2Bitmask = 0xc4,
-  // 0xc5 for relaxed SIMD
-  // 0xc6 for relaxed SIMD
+  // 0xc5 unused
+  // 0xc6 unused
   I64x2ExtendLowI32x4S = 0xc7,
   I64x2ExtendHighI32x4S = 0xc8,
   I64x2ExtendLowI32x4U = 0xc9,
@@ -965,12 +965,12 @@ enum ASTNodes {
   I64x2ShrS = 0xcc,
   I64x2ShrU = 0xcd,
   I64x2Add = 0xce,
-  // 0xcf for relaxed SIMD
-  // 0xd0 for relaxed SIMD
+  // 0xcf unused
+  // 0xd0 unused
   I64x2Sub = 0xd1,
-  // 0xd2 for relaxed SIMD
-  // 0xd3 for relaxed SIMD
-  // 0xd4 for relaxed SIMD
+  // 0xd2 unused
+  // 0xd3 unused
+  // 0xd4 unused
   I64x2Mul = 0xd5,
   I64x2Eq = 0xd6,
   I64x2Ne = 0xd7,
@@ -985,7 +985,7 @@ enum ASTNodes {
 
   F32x4Abs = 0xe0,
   F32x4Neg = 0xe1,
-  // 0xe2 for relaxed SIMD
+  // 0xe2 unused
   F32x4Sqrt = 0xe3,
   F32x4Add = 0xe4,
   F32x4Sub = 0xe5,
@@ -998,7 +998,7 @@ enum ASTNodes {
 
   F64x2Abs = 0xec,
   F64x2Neg = 0xed,
-  // 0xee for relaxed SIMD
+  // 0xee unused
   F64x2Sqrt = 0xef,
   F64x2Add = 0xf0,
   F64x2Sub = 0xf1,
@@ -1019,28 +1019,26 @@ enum ASTNodes {
   F64x2ConvertLowI32x4U = 0xff,
 
   // relaxed SIMD opcodes
-  I8x16RelaxedSwizzle = 0xa2,
-  I32x4RelaxedTruncF32x4S = 0xa5,
-  I32x4RelaxedTruncF32x4U = 0xa6,
-  I32x4RelaxedTruncF64x2SZero = 0xc5,
-  I32x4RelaxedTruncF64x2UZero = 0xc6,
-  F32x4RelaxedFma = 0xaf,
-  F32x4RelaxedFms = 0xb0,
-  F64x2RelaxedFma = 0xcf,
-  F64x2RelaxedFms = 0xd0,
-  I8x16Laneselect = 0xb2,
-  I16x8Laneselect = 0xb3,
-  I32x4Laneselect = 0xd2,
-  I64x2Laneselect = 0xd3,
-  F32x4RelaxedMin = 0xb4,
-  F32x4RelaxedMax = 0xe2,
-  F64x2RelaxedMin = 0xd4,
-  F64x2RelaxedMax = 0xee,
+  I8x16RelaxedSwizzle = 0x100,
+  I32x4RelaxedTruncF32x4S = 0x101,
+  I32x4RelaxedTruncF32x4U = 0x102,
+  I32x4RelaxedTruncF64x2SZero = 0x103,
+  I32x4RelaxedTruncF64x2UZero = 0x104,
+  F32x4RelaxedFma = 0x105,
+  F32x4RelaxedFms = 0x106,
+  F64x2RelaxedFma = 0x107,
+  F64x2RelaxedFms = 0x108,
+  I8x16Laneselect = 0x109,
+  I16x8Laneselect = 0x10a,
+  I32x4Laneselect = 0x10b,
+  I64x2Laneselect = 0x10c,
+  F32x4RelaxedMin = 0x10d,
+  F32x4RelaxedMax = 0x10e,
+  F64x2RelaxedMin = 0x10f,
+  F64x2RelaxedMax = 0x110,
   I16x8RelaxedQ15MulrS = 0x111,
   I16x8DotI8x16I7x16S = 0x112,
-  I16x8DotI8x16I7x16U = 0x113,
-  I32x4DotI8x16I7x16AddS = 0x114,
-  I32x4DotI8x16I7x16AddU = 0x115,
+  I32x4DotI8x16I7x16AddS = 0x113,
 
   // bulk memory opcodes
 
diff --git a/src/wasm-interpreter.h b/src/wasm-interpreter.h
index ef86b35f0..7b17e344b 100644
--- a/src/wasm-interpreter.h
+++ b/src/wasm-interpreter.h
@@ -1018,8 +1018,6 @@ public:
 
       case DotI8x16I7x16SToVecI16x8:
         return left.dotSI8x16toI16x8(right);
-      case DotI8x16I7x16UToVecI16x8:
-        return left.dotUI8x16toI16x8(right);
 
       case InvalidBinary:
         WASM_UNREACHABLE("invalid binary op");
diff --git a/src/wasm.h b/src/wasm.h
index 6e8db91c9..3f2a83460 100644
--- a/src/wasm.h
+++ b/src/wasm.h
@@ -474,7 +474,6 @@ enum BinaryOp {
   RelaxedMaxVecF64x2,
   RelaxedQ15MulrSVecI16x8,
   DotI8x16I7x16SToVecI16x8,
-  DotI8x16I7x16UToVecI16x8,
 
   InvalidBinary
 };
@@ -555,7 +554,6 @@ enum SIMDTernaryOp {
   LaneselectI32x4,
   LaneselectI64x2,
   DotI8x16I7x16AddSToVecI32x4,
-  DotI8x16I7x16AddUToVecI32x4,
 };
 
 enum RefIsOp {
diff --git a/src/wasm/wasm-binary.cpp b/src/wasm/wasm-binary.cpp
index afad575ce..decd78852 100644
--- a/src/wasm/wasm-binary.cpp
+++ b/src/wasm/wasm-binary.cpp
@@ -5619,10 +5619,6 @@ bool WasmBinaryBuilder::maybeVisitSIMDBinary(Expression*& out, uint32_t code) {
       curr = allocator.alloc<Binary>();
       curr->op = DotI8x16I7x16SToVecI16x8;
       break;
-    case BinaryConsts::I16x8DotI8x16I7x16U:
-      curr = allocator.alloc<Binary>();
-      curr->op = DotI8x16I7x16UToVecI16x8;
-      break;
     default:
       return false;
   }
@@ -6101,10 +6097,6 @@ bool WasmBinaryBuilder::maybeVisitSIMDTernary(Expression*& out, uint32_t code) {
       curr = allocator.alloc<SIMDTernary>();
       curr->op = DotI8x16I7x16AddSToVecI32x4;
       break;
-    case BinaryConsts::I32x4DotI8x16I7x16AddU:
-      curr = allocator.alloc<SIMDTernary>();
-      curr->op = DotI8x16I7x16AddUToVecI32x4;
-      break;
     default:
       return false;
   }
diff --git a/src/wasm/wasm-stack.cpp b/src/wasm/wasm-stack.cpp
index 8588a049f..fb24dbb01 100644
--- a/src/wasm/wasm-stack.cpp
+++ b/src/wasm/wasm-stack.cpp
@@ -570,9 +570,6 @@ void BinaryInstWriter::visitSIMDTernary(SIMDTernary* curr) {
     case DotI8x16I7x16AddSToVecI32x4:
       o << U32LEB(BinaryConsts::I32x4DotI8x16I7x16AddS);
       break;
-    case DotI8x16I7x16AddUToVecI32x4:
-      o << U32LEB(BinaryConsts::I32x4DotI8x16I7x16AddU);
-      break;
   }
 }
 
@@ -1853,10 +1850,6 @@ void BinaryInstWriter::visitBinary(Binary* curr) {
       o << int8_t(BinaryConsts::SIMDPrefix)
         << U32LEB(BinaryConsts::I16x8DotI8x16I7x16S);
       break;
-    case DotI8x16I7x16UToVecI16x8:
-      o << int8_t(BinaryConsts::SIMDPrefix)
-        << U32LEB(BinaryConsts::I16x8DotI8x16I7x16U);
-      break;
 
     case InvalidBinary:
       WASM_UNREACHABLE("invalid binary op");
diff --git a/src/wasm/wasm-validator.cpp b/src/wasm/wasm-validator.cpp
index 57b52e182..54bc2f9d4 100644
--- a/src/wasm/wasm-validator.cpp
+++ b/src/wasm/wasm-validator.cpp
@@ -1636,8 +1636,7 @@ void FunctionValidator::visitBinary(Binary* curr) {
     case SwizzleVecI8x16:
     case RelaxedSwizzleVecI8x16:
     case RelaxedQ15MulrSVecI16x8:
-    case DotI8x16I7x16SToVecI16x8:
-    case DotI8x16I7x16UToVecI16x8: {
+    case DotI8x16I7x16SToVecI16x8: {
       shouldBeEqualOrFirstIsUnreachable(
         curr->left->type, Type(Type::v128), curr, "v128 op");
       shouldBeEqualOrFirstIsUnreachable(