Rename relaxed SIMD fma instructions to match spec. (#6876)

The instructions relaxed_fma and relaxed_fnma have been renamed to
relaxed_madd and relaxed_nmadd.


https://github.com/WebAssembly/relaxed-simd/blob/main/proposals/relaxed-simd/Overview.md#binary-format

13 files changed, 124 insertions, 120 deletions

diff --git a/src/binaryen-c.cpp b/src/binaryen-c.cpp
index afc3dbe54..31378ce22 100644
--- a/src/binaryen-c.cpp
+++ b/src/binaryen-c.cpp
@@ -755,10 +755,10 @@ BinaryenOp BinaryenOrVec128(void) { return OrVec128; }
 BinaryenOp BinaryenXorVec128(void) { return XorVec128; }
 BinaryenOp BinaryenAndNotVec128(void) { return AndNotVec128; }
 BinaryenOp BinaryenBitselectVec128(void) { return Bitselect; }
-BinaryenOp BinaryenRelaxedFmaVecF32x4(void) { return RelaxedFmaVecF32x4; }
-BinaryenOp BinaryenRelaxedFmsVecF32x4(void) { return RelaxedFmsVecF32x4; }
-BinaryenOp BinaryenRelaxedFmaVecF64x2(void) { return RelaxedFmaVecF64x2; }
-BinaryenOp BinaryenRelaxedFmsVecF64x2(void) { return RelaxedFmsVecF64x2; }
+BinaryenOp BinaryenRelaxedMaddVecF32x4(void) { return RelaxedMaddVecF32x4; }
+BinaryenOp BinaryenRelaxedNmaddVecF32x4(void) { return RelaxedNmaddVecF32x4; }
+BinaryenOp BinaryenRelaxedMaddVecF64x2(void) { return RelaxedMaddVecF64x2; }
+BinaryenOp BinaryenRelaxedNmaddVecF64x2(void) { return RelaxedNmaddVecF64x2; }
 BinaryenOp BinaryenLaneselectI8x16(void) { return LaneselectI8x16; }
 BinaryenOp BinaryenLaneselectI16x8(void) { return LaneselectI16x8; }
 BinaryenOp BinaryenLaneselectI32x4(void) { return LaneselectI32x4; }
diff --git a/src/binaryen-c.h b/src/binaryen-c.h
index 0b1319f30..b23945d18 100644
--- a/src/binaryen-c.h
+++ b/src/binaryen-c.h
@@ -497,10 +497,10 @@ BINARYEN_API BinaryenOp BinaryenOrVec128(void);
 BINARYEN_API BinaryenOp BinaryenXorVec128(void);
 BINARYEN_API BinaryenOp BinaryenAndNotVec128(void);
 BINARYEN_API BinaryenOp BinaryenBitselectVec128(void);
-BINARYEN_API BinaryenOp BinaryenRelaxedFmaVecF32x4(void);
-BINARYEN_API BinaryenOp BinaryenRelaxedFmsVecF32x4(void);
-BINARYEN_API BinaryenOp BinaryenRelaxedFmaVecF64x2(void);
-BINARYEN_API BinaryenOp BinaryenRelaxedFmsVecF64x2(void);
+BINARYEN_API BinaryenOp BinaryenRelaxedMaddVecF32x4(void);
+BINARYEN_API BinaryenOp BinaryenRelaxedNmaddVecF32x4(void);
+BINARYEN_API BinaryenOp BinaryenRelaxedMaddVecF64x2(void);
+BINARYEN_API BinaryenOp BinaryenRelaxedNmaddVecF64x2(void);
 BINARYEN_API BinaryenOp BinaryenLaneselectI8x16(void);
 BINARYEN_API BinaryenOp BinaryenLaneselectI16x8(void);
 BINARYEN_API BinaryenOp BinaryenLaneselectI32x4(void);
diff --git a/src/gen-s-parser.inc b/src/gen-s-parser.inc
index 7d4fbe819..56a7c1cce 100644
--- a/src/gen-s-parser.inc
+++ b/src/gen-s-parser.inc
@@ -952,31 +952,25 @@ switch (buf[0]) {
                 switch (buf[8]) {
                   case 'l': {
                     switch (buf[14]) {
-                      case 'f': {
-                        switch (buf[16]) {
-                          case 'a':
-                            if (op == "f32x4.relaxed_fma"sv) {
-                              CHECK_ERR(makeSIMDTernary(ctx, pos, annotations, SIMDTernaryOp::RelaxedFmaVecF32x4));
-                              return Ok{};
-                            }
-                            goto parse_error;
-                          case 's':
-                            if (op == "f32x4.relaxed_fms"sv) {
-                              CHECK_ERR(makeSIMDTernary(ctx, pos, annotations, SIMDTernaryOp::RelaxedFmsVecF32x4));
-                              return Ok{};
-                            }
-                            goto parse_error;
-                          default: goto parse_error;
-                        }
-                      }
                       case 'm': {
                         switch (buf[15]) {
-                          case 'a':
-                            if (op == "f32x4.relaxed_max"sv) {
-                              CHECK_ERR(makeBinary(ctx, pos, annotations, BinaryOp::RelaxedMaxVecF32x4));
-                              return Ok{};
+                          case 'a': {
+                            switch (buf[16]) {
+                              case 'd':
+                                if (op == "f32x4.relaxed_madd"sv) {
+                                  CHECK_ERR(makeSIMDTernary(ctx, pos, annotations, SIMDTernaryOp::RelaxedMaddVecF32x4));
+                                  return Ok{};
+                                }
+                                goto parse_error;
+                              case 'x':
+                                if (op == "f32x4.relaxed_max"sv) {
+                                  CHECK_ERR(makeBinary(ctx, pos, annotations, BinaryOp::RelaxedMaxVecF32x4));
+                                  return Ok{};
+                                }
+                                goto parse_error;
+                              default: goto parse_error;
                             }
-                            goto parse_error;
+                          }
                           case 'i':
                             if (op == "f32x4.relaxed_min"sv) {
                               CHECK_ERR(makeBinary(ctx, pos, annotations, BinaryOp::RelaxedMinVecF32x4));
@@ -986,6 +980,12 @@ switch (buf[0]) {
                           default: goto parse_error;
                         }
                       }
+                      case 'n':
+                        if (op == "f32x4.relaxed_nmadd"sv) {
+                          CHECK_ERR(makeSIMDTernary(ctx, pos, annotations, SIMDTernaryOp::RelaxedNmaddVecF32x4));
+                          return Ok{};
+                        }
+                        goto parse_error;
                       default: goto parse_error;
                     }
                   }
@@ -1462,31 +1462,25 @@ switch (buf[0]) {
                 switch (buf[8]) {
                   case 'l': {
                     switch (buf[14]) {
-                      case 'f': {
-                        switch (buf[16]) {
-                          case 'a':
-                            if (op == "f64x2.relaxed_fma"sv) {
-                              CHECK_ERR(makeSIMDTernary(ctx, pos, annotations, SIMDTernaryOp::RelaxedFmaVecF64x2));
-                              return Ok{};
-                            }
-                            goto parse_error;
-                          case 's':
-                            if (op == "f64x2.relaxed_fms"sv) {
-                              CHECK_ERR(makeSIMDTernary(ctx, pos, annotations, SIMDTernaryOp::RelaxedFmsVecF64x2));
-                              return Ok{};
-                            }
-                            goto parse_error;
-                          default: goto parse_error;
-                        }
-                      }
                       case 'm': {
                         switch (buf[15]) {
-                          case 'a':
-                            if (op == "f64x2.relaxed_max"sv) {
-                              CHECK_ERR(makeBinary(ctx, pos, annotations, BinaryOp::RelaxedMaxVecF64x2));
-                              return Ok{};
+                          case 'a': {
+                            switch (buf[16]) {
+                              case 'd':
+                                if (op == "f64x2.relaxed_madd"sv) {
+                                  CHECK_ERR(makeSIMDTernary(ctx, pos, annotations, SIMDTernaryOp::RelaxedMaddVecF64x2));
+                                  return Ok{};
+                                }
+                                goto parse_error;
+                              case 'x':
+                                if (op == "f64x2.relaxed_max"sv) {
+                                  CHECK_ERR(makeBinary(ctx, pos, annotations, BinaryOp::RelaxedMaxVecF64x2));
+                                  return Ok{};
+                                }
+                                goto parse_error;
+                              default: goto parse_error;
                             }
-                            goto parse_error;
+                          }
                           case 'i':
                             if (op == "f64x2.relaxed_min"sv) {
                               CHECK_ERR(makeBinary(ctx, pos, annotations, BinaryOp::RelaxedMinVecF64x2));
@@ -1496,6 +1490,12 @@ switch (buf[0]) {
                           default: goto parse_error;
                         }
                       }
+                      case 'n':
+                        if (op == "f64x2.relaxed_nmadd"sv) {
+                          CHECK_ERR(makeSIMDTernary(ctx, pos, annotations, SIMDTernaryOp::RelaxedNmaddVecF64x2));
+                          return Ok{};
+                        }
+                        goto parse_error;
                       default: goto parse_error;
                     }
                   }
diff --git a/src/ir/cost.h b/src/ir/cost.h
index f541a4506..99b945815 100644
--- a/src/ir/cost.h
+++ b/src/ir/cost.h
@@ -582,10 +582,10 @@ struct CostAnalyzer : public OverriddenVisitor<CostAnalyzer, CostType> {
       case LaneselectI16x8:
       case LaneselectI32x4:
       case LaneselectI64x2:
-      case RelaxedFmaVecF32x4:
-      case RelaxedFmsVecF32x4:
-      case RelaxedFmaVecF64x2:
-      case RelaxedFmsVecF64x2:
+      case RelaxedMaddVecF32x4:
+      case RelaxedNmaddVecF32x4:
+      case RelaxedMaddVecF64x2:
+      case RelaxedNmaddVecF64x2:
       case DotI8x16I7x16AddSToVecI32x4:
         ret = 1;
         break;
diff --git a/src/js/binaryen.js-post.js b/src/js/binaryen.js-post.js
index 55e1a7ad7..40d08dceb 100644
--- a/src/js/binaryen.js-post.js
+++ b/src/js/binaryen.js-post.js
@@ -383,10 +383,10 @@ function initializeConstants() {
     'XorVec128',
     'AndNotVec128',
     'BitselectVec128',
-    'RelaxedFmaVecF32x4',
-    'RelaxedFmsVecF32x4',
-    'RelaxedFmaVecF64x2',
-    'RelaxedFmsVecF64x2',
+    'RelaxedMaddVecF32x4',
+    'RelaxedNmaddVecF32x4',
+    'RelaxedMaddVecF64x2',
+    'RelaxedNmaddVecF64x2',
     'LaneselectI8x16',
     'LaneselectI16x8',
     'LaneselectI32x4',
diff --git a/src/literal.h b/src/literal.h
index 7bedab5b4..73289c83b 100644
--- a/src/literal.h
+++ b/src/literal.h
@@ -442,8 +442,8 @@ public:
 
   // Fused multiply add and subtract.
   // Computes this + (left * right) to infinite precision then round once.
-  Literal fma(const Literal& left, const Literal& right) const;
-  Literal fms(const Literal& left, const Literal& right) const;
+  Literal madd(const Literal& left, const Literal& right) const;
+  Literal nmadd(const Literal& left, const Literal& right) const;
 
   std::array<Literal, 16> getLanesSI8x16() const;
   std::array<Literal, 16> getLanesUI8x16() const;
@@ -694,10 +694,10 @@ public:
   Literal demoteZeroToF32x4() const;
   Literal promoteLowToF64x2() const;
   Literal swizzleI8x16(const Literal& other) const;
-  Literal relaxedFmaF32x4(const Literal& left, const Literal& right) const;
-  Literal relaxedFmsF32x4(const Literal& left, const Literal& right) const;
-  Literal relaxedFmaF64x2(const Literal& left, const Literal& right) const;
-  Literal relaxedFmsF64x2(const Literal& left, const Literal& right) const;
+  Literal relaxedMaddF32x4(const Literal& left, const Literal& right) const;
+  Literal relaxedNmaddF32x4(const Literal& left, const Literal& right) const;
+  Literal relaxedMaddF64x2(const Literal& left, const Literal& right) const;
+  Literal relaxedNmaddF64x2(const Literal& left, const Literal& right) const;
 
   Literal externalize() const;
   Literal internalize() const;
diff --git a/src/passes/Print.cpp b/src/passes/Print.cpp
index 8f53481b7..024b6af5c 100644
--- a/src/passes/Print.cpp
+++ b/src/passes/Print.cpp
@@ -770,17 +770,17 @@ struct PrintExpressionContents
       case LaneselectI64x2:
         o << "i64x2.laneselect";
         break;
-      case RelaxedFmaVecF32x4:
-        o << "f32x4.relaxed_fma";
+      case RelaxedMaddVecF32x4:
+        o << "f32x4.relaxed_madd";
         break;
-      case RelaxedFmsVecF32x4:
-        o << "f32x4.relaxed_fms";
+      case RelaxedNmaddVecF32x4:
+        o << "f32x4.relaxed_nmadd";
         break;
-      case RelaxedFmaVecF64x2:
-        o << "f64x2.relaxed_fma";
+      case RelaxedMaddVecF64x2:
+        o << "f64x2.relaxed_madd";
         break;
-      case RelaxedFmsVecF64x2:
-        o << "f64x2.relaxed_fms";
+      case RelaxedNmaddVecF64x2:
+        o << "f64x2.relaxed_nmadd";
         break;
       case DotI8x16I7x16AddSToVecI32x4:
         o << "i32x4.dot_i8x16_i7x16_add_s";
diff --git a/src/wasm-binary.h b/src/wasm-binary.h
index 9ce355b48..e8ed293e7 100644
--- a/src/wasm-binary.h
+++ b/src/wasm-binary.h
@@ -1037,10 +1037,10 @@ enum ASTNodes {
   I32x4RelaxedTruncF32x4U = 0x102,
   I32x4RelaxedTruncF64x2SZero = 0x103,
   I32x4RelaxedTruncF64x2UZero = 0x104,
-  F32x4RelaxedFma = 0x105,
-  F32x4RelaxedFms = 0x106,
-  F64x2RelaxedFma = 0x107,
-  F64x2RelaxedFms = 0x108,
+  F32x4RelaxedMadd = 0x105,
+  F32x4RelaxedNmadd = 0x106,
+  F64x2RelaxedMadd = 0x107,
+  F64x2RelaxedNmadd = 0x108,
   I8x16Laneselect = 0x109,
   I16x8Laneselect = 0x10a,
   I32x4Laneselect = 0x10b,
diff --git a/src/wasm-interpreter.h b/src/wasm-interpreter.h
index 50fc296fe..578b0a569 100644
--- a/src/wasm-interpreter.h
+++ b/src/wasm-interpreter.h
@@ -1201,14 +1201,14 @@ public:
       case LaneselectI64x2:
         return c.bitselectV128(a, b);
 
-      case RelaxedFmaVecF32x4:
-        return a.relaxedFmaF32x4(b, c);
-      case RelaxedFmsVecF32x4:
-        return a.relaxedFmsF32x4(b, c);
-      case RelaxedFmaVecF64x2:
-        return a.relaxedFmaF64x2(b, c);
-      case RelaxedFmsVecF64x2:
-        return a.relaxedFmsF64x2(b, c);
+      case RelaxedMaddVecF32x4:
+        return a.relaxedMaddF32x4(b, c);
+      case RelaxedNmaddVecF32x4:
+        return a.relaxedNmaddF32x4(b, c);
+      case RelaxedMaddVecF64x2:
+        return a.relaxedMaddF64x2(b, c);
+      case RelaxedNmaddVecF64x2:
+        return a.relaxedNmaddF64x2(b, c);
       default:
         // TODO: implement signselect and dot_add
         WASM_UNREACHABLE("not implemented");
diff --git a/src/wasm.h b/src/wasm.h
index a707ab7a4..86ee12972 100644
--- a/src/wasm.h
+++ b/src/wasm.h
@@ -574,10 +574,10 @@ enum SIMDTernaryOp {
   Bitselect,
 
   // Relaxed SIMD
-  RelaxedFmaVecF32x4,
-  RelaxedFmsVecF32x4,
-  RelaxedFmaVecF64x2,
-  RelaxedFmsVecF64x2,
+  RelaxedMaddVecF32x4,
+  RelaxedNmaddVecF32x4,
+  RelaxedMaddVecF64x2,
+  RelaxedNmaddVecF64x2,
   LaneselectI8x16,
   LaneselectI16x8,
   LaneselectI32x4,
diff --git a/src/wasm/literal.cpp b/src/wasm/literal.cpp
index 1b84ba53c..c76856d15 100644
--- a/src/wasm/literal.cpp
+++ b/src/wasm/literal.cpp
@@ -1671,7 +1671,7 @@ Literal Literal::copysign(const Literal& other) const {
   }
 }
 
-Literal Literal::fma(const Literal& left, const Literal& right) const {
+Literal Literal::madd(const Literal& left, const Literal& right) const {
   switch (type.getBasic()) {
     case Type::f32:
       return Literal(::fmaf(left.getf32(), right.getf32(), getf32()));
@@ -1684,7 +1684,7 @@ Literal Literal::fma(const Literal& left, const Literal& right) const {
   }
 }
 
-Literal Literal::fms(const Literal& left, const Literal& right) const {
+Literal Literal::nmadd(const Literal& left, const Literal& right) const {
   switch (type.getBasic()) {
     case Type::f32:
       return Literal(::fmaf(-left.getf32(), right.getf32(), getf32()));
@@ -2762,24 +2762,28 @@ static Literal ternary(const Literal& a, const Literal& b, const Literal& c) {
 }
 } // namespace
 
-Literal Literal::relaxedFmaF32x4(const Literal& left,
-                                 const Literal& right) const {
-  return ternary<4, &Literal::getLanesF32x4, &Literal::fma>(*this, left, right);
+Literal Literal::relaxedMaddF32x4(const Literal& left,
+                                  const Literal& right) const {
+  return ternary<4, &Literal::getLanesF32x4, &Literal::madd>(
+    *this, left, right);
 }
 
-Literal Literal::relaxedFmsF32x4(const Literal& left,
-                                 const Literal& right) const {
-  return ternary<4, &Literal::getLanesF32x4, &Literal::fms>(*this, left, right);
+Literal Literal::relaxedNmaddF32x4(const Literal& left,
+                                   const Literal& right) const {
+  return ternary<4, &Literal::getLanesF32x4, &Literal::nmadd>(
+    *this, left, right);
 }
 
-Literal Literal::relaxedFmaF64x2(const Literal& left,
-                                 const Literal& right) const {
-  return ternary<2, &Literal::getLanesF64x2, &Literal::fma>(*this, left, right);
+Literal Literal::relaxedMaddF64x2(const Literal& left,
+                                  const Literal& right) const {
+  return ternary<2, &Literal::getLanesF64x2, &Literal::madd>(
+    *this, left, right);
 }
 
-Literal Literal::relaxedFmsF64x2(const Literal& left,
-                                 const Literal& right) const {
-  return ternary<2, &Literal::getLanesF64x2, &Literal::fms>(*this, left, right);
+Literal Literal::relaxedNmaddF64x2(const Literal& left,
+                                   const Literal& right) const {
+  return ternary<2, &Literal::getLanesF64x2, &Literal::nmadd>(
+    *this, left, right);
 }
 
 Literal Literal::externalize() const {
diff --git a/src/wasm/wasm-binary.cpp b/src/wasm/wasm-binary.cpp
index 16a926182..8c684dc2f 100644
--- a/src/wasm/wasm-binary.cpp
+++ b/src/wasm/wasm-binary.cpp
@@ -6823,21 +6823,21 @@ bool WasmBinaryReader::maybeVisitSIMDTernary(Expression*& out, uint32_t code) {
       curr = allocator.alloc<SIMDTernary>();
       curr->op = LaneselectI64x2;
       break;
-    case BinaryConsts::F32x4RelaxedFma:
+    case BinaryConsts::F32x4RelaxedMadd:
       curr = allocator.alloc<SIMDTernary>();
-      curr->op = RelaxedFmaVecF32x4;
+      curr->op = RelaxedMaddVecF32x4;
       break;
-    case BinaryConsts::F32x4RelaxedFms:
+    case BinaryConsts::F32x4RelaxedNmadd:
       curr = allocator.alloc<SIMDTernary>();
-      curr->op = RelaxedFmsVecF32x4;
+      curr->op = RelaxedNmaddVecF32x4;
       break;
-    case BinaryConsts::F64x2RelaxedFma:
+    case BinaryConsts::F64x2RelaxedMadd:
       curr = allocator.alloc<SIMDTernary>();
-      curr->op = RelaxedFmaVecF64x2;
+      curr->op = RelaxedMaddVecF64x2;
       break;
-    case BinaryConsts::F64x2RelaxedFms:
+    case BinaryConsts::F64x2RelaxedNmadd:
       curr = allocator.alloc<SIMDTernary>();
-      curr->op = RelaxedFmsVecF64x2;
+      curr->op = RelaxedNmaddVecF64x2;
       break;
     case BinaryConsts::I32x4DotI8x16I7x16AddS:
       curr = allocator.alloc<SIMDTernary>();
diff --git a/src/wasm/wasm-stack.cpp b/src/wasm/wasm-stack.cpp
index 59593ddde..140205b85 100644
--- a/src/wasm/wasm-stack.cpp
+++ b/src/wasm/wasm-stack.cpp
@@ -657,17 +657,17 @@ void BinaryInstWriter::visitSIMDTernary(SIMDTernary* curr) {
     case LaneselectI64x2:
       o << U32LEB(BinaryConsts::I64x2Laneselect);
       break;
-    case RelaxedFmaVecF32x4:
-      o << U32LEB(BinaryConsts::F32x4RelaxedFma);
+    case RelaxedMaddVecF32x4:
+      o << U32LEB(BinaryConsts::F32x4RelaxedMadd);
       break;
-    case RelaxedFmsVecF32x4:
-      o << U32LEB(BinaryConsts::F32x4RelaxedFms);
+    case RelaxedNmaddVecF32x4:
+      o << U32LEB(BinaryConsts::F32x4RelaxedNmadd);
       break;
-    case RelaxedFmaVecF64x2:
-      o << U32LEB(BinaryConsts::F64x2RelaxedFma);
+    case RelaxedMaddVecF64x2:
+      o << U32LEB(BinaryConsts::F64x2RelaxedMadd);
       break;
-    case RelaxedFmsVecF64x2:
-      o << U32LEB(BinaryConsts::F64x2RelaxedFms);
+    case RelaxedNmaddVecF64x2:
+      o << U32LEB(BinaryConsts::F64x2RelaxedNmadd);
       break;
     case DotI8x16I7x16AddSToVecI32x4:
       o << U32LEB(BinaryConsts::I32x4DotI8x16I7x16AddS);