diff options
Diffstat (limited to 'scripts/gen-s-parser.py')
| -rwxr-xr-x | scripts/gen-s-parser.py | 143 |
1 files changed, 142 insertions, 1 deletions
diff --git a/scripts/gen-s-parser.py b/scripts/gen-s-parser.py index f33107ea6..ea96f3d49 100755 --- a/scripts/gen-s-parser.py +++ b/scripts/gen-s-parser.py @@ -268,6 +268,147 @@ instructions = [ ("i64.trunc_u:sat/f32", "makeUnary(s, UnaryOp::TruncSatUFloat32ToInt64)"), ("i64.trunc_s:sat/f64", "makeUnary(s, UnaryOp::TruncSatSFloat64ToInt64)"), ("i64.trunc_u:sat/f64", "makeUnary(s, UnaryOp::TruncSatUFloat64ToInt64)"), + # SIMD ops + ("v128.load", "makeLoad(s, v128, /*isAtomic=*/false)"), + ("v128.store", "makeStore(s, v128, /*isAtomic=*/false)"), + ("v128.const", "makeConst(s, v128)"), + ("v8x16.shuffle", "makeSIMDShuffle(s)"), + ("i8x16.splat", "makeUnary(s, UnaryOp::SplatVecI8x16)"), + ("i8x16.extract_lane_s", "makeSIMDExtract(s, SIMDExtractOp::ExtractLaneSVecI8x16, 16)"), + ("i8x16.extract_lane_u", "makeSIMDExtract(s, SIMDExtractOp::ExtractLaneUVecI8x16, 16)"), + ("i8x16.replace_lane", "makeSIMDReplace(s, SIMDReplaceOp::ReplaceLaneVecI8x16, 16)"), + ("i16x8.splat", "makeUnary(s, UnaryOp::SplatVecI16x8)"), + ("i16x8.extract_lane_s", "makeSIMDExtract(s, SIMDExtractOp::ExtractLaneSVecI16x8, 8)"), + ("i16x8.extract_lane_u", "makeSIMDExtract(s, SIMDExtractOp::ExtractLaneUVecI16x8, 8)"), + ("i16x8.replace_lane", "makeSIMDReplace(s, SIMDReplaceOp::ReplaceLaneVecI16x8, 8)"), + ("i32x4.splat", "makeUnary(s, UnaryOp::SplatVecI32x4)"), + ("i32x4.extract_lane", "makeSIMDExtract(s, SIMDExtractOp::ExtractLaneVecI32x4, 4)"), + ("i32x4.replace_lane", "makeSIMDReplace(s, SIMDReplaceOp::ReplaceLaneVecI32x4, 4)"), + ("i64x2.splat", "makeUnary(s, UnaryOp::SplatVecI64x2)"), + ("i64x2.extract_lane", "makeSIMDExtract(s, SIMDExtractOp::ExtractLaneVecI64x2, 2)"), + ("i64x2.replace_lane", "makeSIMDReplace(s, SIMDReplaceOp::ReplaceLaneVecI64x2, 2)"), + ("f32x4.splat", "makeUnary(s, UnaryOp::SplatVecF32x4)"), + ("f32x4.extract_lane", "makeSIMDExtract(s, SIMDExtractOp::ExtractLaneVecF32x4, 4)"), + ("f32x4.replace_lane", "makeSIMDReplace(s, SIMDReplaceOp::ReplaceLaneVecF32x4, 4)"), + ("f64x2.splat", "makeUnary(s, UnaryOp::SplatVecF64x2)"), + ("f64x2.extract_lane", "makeSIMDExtract(s, SIMDExtractOp::ExtractLaneVecF64x2, 2)"), + ("f64x2.replace_lane", "makeSIMDReplace(s, SIMDReplaceOp::ReplaceLaneVecF64x2, 2)"), + ("i8x16.eq", "makeBinary(s, BinaryOp::EqVecI8x16)"), + ("i8x16.ne", "makeBinary(s, BinaryOp::NeVecI8x16)"), + ("i8x16.lt_s", "makeBinary(s, BinaryOp::LtSVecI8x16)"), + ("i8x16.lt_u", "makeBinary(s, BinaryOp::LtUVecI8x16)"), + ("i8x16.gt_s", "makeBinary(s, BinaryOp::GtSVecI8x16)"), + ("i8x16.gt_u", "makeBinary(s, BinaryOp::GtUVecI8x16)"), + ("i8x16.le_s", "makeBinary(s, BinaryOp::LeSVecI8x16)"), + ("i8x16.le_u", "makeBinary(s, BinaryOp::LeUVecI8x16)"), + ("i8x16.ge_s", "makeBinary(s, BinaryOp::GeSVecI8x16)"), + ("i8x16.ge_u", "makeBinary(s, BinaryOp::GeUVecI8x16)"), + ("i16x8.eq", "makeBinary(s, BinaryOp::EqVecI16x8)"), + ("i16x8.ne", "makeBinary(s, BinaryOp::NeVecI16x8)"), + ("i16x8.lt_s", "makeBinary(s, BinaryOp::LtSVecI16x8)"), + ("i16x8.lt_u", "makeBinary(s, BinaryOp::LtUVecI16x8)"), + ("i16x8.gt_s", "makeBinary(s, BinaryOp::GtSVecI16x8)"), + ("i16x8.gt_u", "makeBinary(s, BinaryOp::GtUVecI16x8)"), + ("i16x8.le_s", "makeBinary(s, BinaryOp::LeSVecI16x8)"), + ("i16x8.le_u", "makeBinary(s, BinaryOp::LeUVecI16x8)"), + ("i16x8.ge_s", "makeBinary(s, BinaryOp::GeSVecI16x8)"), + ("i16x8.ge_u", "makeBinary(s, BinaryOp::GeUVecI16x8)"), + ("i32x4.eq", "makeBinary(s, BinaryOp::EqVecI32x4)"), + ("i32x4.ne", "makeBinary(s, BinaryOp::NeVecI32x4)"), + ("i32x4.lt_s", "makeBinary(s, BinaryOp::LtSVecI32x4)"), + ("i32x4.lt_u", "makeBinary(s, BinaryOp::LtUVecI32x4)"), + ("i32x4.gt_s", "makeBinary(s, BinaryOp::GtSVecI32x4)"), + ("i32x4.gt_u", "makeBinary(s, BinaryOp::GtUVecI32x4)"), + ("i32x4.le_s", "makeBinary(s, BinaryOp::LeSVecI32x4)"), + ("i32x4.le_u", "makeBinary(s, BinaryOp::LeUVecI32x4)"), + ("i32x4.ge_s", "makeBinary(s, BinaryOp::GeSVecI32x4)"), + ("i32x4.ge_u", "makeBinary(s, BinaryOp::GeUVecI32x4)"), + ("f32x4.eq", "makeBinary(s, BinaryOp::EqVecF32x4)"), + ("f32x4.ne", "makeBinary(s, BinaryOp::NeVecF32x4)"), + ("f32x4.lt", "makeBinary(s, BinaryOp::LtVecF32x4)"), + ("f32x4.gt", "makeBinary(s, BinaryOp::GtVecF32x4)"), + ("f32x4.le", "makeBinary(s, BinaryOp::LeVecF32x4)"), + ("f32x4.ge", "makeBinary(s, BinaryOp::GeVecF32x4)"), + ("f64x2.eq", "makeBinary(s, BinaryOp::EqVecF64x2)"), + ("f64x2.ne", "makeBinary(s, BinaryOp::NeVecF64x2)"), + ("f64x2.lt", "makeBinary(s, BinaryOp::LtVecF64x2)"), + ("f64x2.gt", "makeBinary(s, BinaryOp::GtVecF64x2)"), + ("f64x2.le", "makeBinary(s, BinaryOp::LeVecF64x2)"), + ("f64x2.ge", "makeBinary(s, BinaryOp::GeVecF64x2)"), + ("v128.not", "makeUnary(s, UnaryOp::NotVec128)"), + ("v128.and", "makeBinary(s, BinaryOp::AndVec128)"), + ("v128.or", "makeBinary(s, BinaryOp::OrVec128)"), + ("v128.xor", "makeBinary(s, BinaryOp::XorVec128)"), + ("v128.bitselect", "makeSIMDBitselect(s)"), + ("i8x16.neg", "makeUnary(s, UnaryOp::NegVecI8x16)"), + ("i8x16.any_true", "makeUnary(s, UnaryOp::AnyTrueVecI8x16)"), + ("i8x16.all_true", "makeUnary(s, UnaryOp::AllTrueVecI8x16)"), + ("i8x16.shl", "makeSIMDShift(s, SIMDShiftOp::ShlVecI8x16)"), + ("i8x16.shr_s", "makeSIMDShift(s, SIMDShiftOp::ShrSVecI8x16)"), + ("i8x16.shr_u", "makeSIMDShift(s, SIMDShiftOp::ShrUVecI8x16)"), + ("i8x16.add", "makeBinary(s, BinaryOp::AddVecI8x16)"), + ("i8x16.add_saturate_s", "makeBinary(s, BinaryOp::AddSatSVecI8x16)"), + ("i8x16.add_saturate_u", "makeBinary(s, BinaryOp::AddSatUVecI8x16)"), + ("i8x16.sub", "makeBinary(s, BinaryOp::SubVecI8x16)"), + ("i8x16.sub_saturate_s", "makeBinary(s, BinaryOp::SubSatSVecI8x16)"), + ("i8x16.sub_saturate_u", "makeBinary(s, BinaryOp::SubSatUVecI8x16)"), + ("i8x16.mul", "makeBinary(s, BinaryOp::MulVecI8x16)"), + ("i16x8.neg", "makeUnary(s, UnaryOp::NegVecI16x8)"), + ("i16x8.any_true", "makeUnary(s, UnaryOp::AnyTrueVecI16x8)"), + ("i16x8.all_true", "makeUnary(s, UnaryOp::AllTrueVecI16x8)"), + ("i16x8.shl", "makeSIMDShift(s, SIMDShiftOp::ShlVecI16x8)"), + ("i16x8.shr_s", "makeSIMDShift(s, SIMDShiftOp::ShrSVecI16x8)"), + ("i16x8.shr_u", "makeSIMDShift(s, SIMDShiftOp::ShrUVecI16x8)"), + ("i16x8.add", "makeBinary(s, BinaryOp::AddVecI16x8)"), + ("i16x8.add_saturate_s", "makeBinary(s, BinaryOp::AddSatSVecI16x8)"), + ("i16x8.add_saturate_u", "makeBinary(s, BinaryOp::AddSatUVecI16x8)"), + ("i16x8.sub", "makeBinary(s, BinaryOp::SubVecI16x8)"), + ("i16x8.sub_saturate_s", "makeBinary(s, BinaryOp::SubSatSVecI16x8)"), + ("i16x8.sub_saturate_u", "makeBinary(s, BinaryOp::SubSatUVecI16x8)"), + ("i16x8.mul", "makeBinary(s, BinaryOp::MulVecI16x8)"), + ("i32x4.neg", "makeUnary(s, UnaryOp::NegVecI32x4)"), + ("i32x4.any_true", "makeUnary(s, UnaryOp::AnyTrueVecI32x4)"), + ("i32x4.all_true", "makeUnary(s, UnaryOp::AllTrueVecI32x4)"), + ("i32x4.shl", "makeSIMDShift(s, SIMDShiftOp::ShlVecI32x4)"), + ("i32x4.shr_s", "makeSIMDShift(s, SIMDShiftOp::ShrSVecI32x4)"), + ("i32x4.shr_u", "makeSIMDShift(s, SIMDShiftOp::ShrUVecI32x4)"), + ("i32x4.add", "makeBinary(s, BinaryOp::AddVecI32x4)"), + ("i32x4.sub", "makeBinary(s, BinaryOp::SubVecI32x4)"), + ("i32x4.mul", "makeBinary(s, BinaryOp::MulVecI32x4)"), + ("i64x2.neg", "makeUnary(s, UnaryOp::NegVecI64x2)"), + ("i64x2.any_true", "makeUnary(s, UnaryOp::AnyTrueVecI64x2)"), + ("i64x2.all_true", "makeUnary(s, UnaryOp::AllTrueVecI64x2)"), + ("i64x2.shl", "makeSIMDShift(s, SIMDShiftOp::ShlVecI64x2)"), + ("i64x2.shr_s", "makeSIMDShift(s, SIMDShiftOp::ShrSVecI64x2)"), + ("i64x2.shr_u", "makeSIMDShift(s, SIMDShiftOp::ShrUVecI64x2)"), + ("i64x2.add", "makeBinary(s, BinaryOp::AddVecI64x2)"), + ("i64x2.sub", "makeBinary(s, BinaryOp::SubVecI64x2)"), + ("f32x4.abs", "makeUnary(s, UnaryOp::AbsVecF32x4)"), + ("f32x4.neg", "makeUnary(s, UnaryOp::NegVecF32x4)"), + ("f32x4.sqrt", "makeUnary(s, UnaryOp::SqrtVecF32x4)"), + ("f32x4.add", "makeBinary(s, BinaryOp::AddVecF32x4)"), + ("f32x4.sub", "makeBinary(s, BinaryOp::SubVecF32x4)"), + ("f32x4.mul", "makeBinary(s, BinaryOp::MulVecF32x4)"), + ("f32x4.div", "makeBinary(s, BinaryOp::DivVecF32x4)"), + ("f32x4.min", "makeBinary(s, BinaryOp::MinVecF32x4)"), + ("f32x4.max", "makeBinary(s, BinaryOp::MaxVecF32x4)"), + ("f64x2.abs", "makeUnary(s, UnaryOp::AbsVecF64x2)"), + ("f64x2.neg", "makeUnary(s, UnaryOp::NegVecF64x2)"), + ("f64x2.sqrt", "makeUnary(s, UnaryOp::SqrtVecF64x2)"), + ("f64x2.add", "makeBinary(s, BinaryOp::AddVecF64x2)"), + ("f64x2.sub", "makeBinary(s, BinaryOp::SubVecF64x2)"), + ("f64x2.mul", "makeBinary(s, BinaryOp::MulVecF64x2)"), + ("f64x2.div", "makeBinary(s, BinaryOp::DivVecF64x2)"), + ("f64x2.min", "makeBinary(s, BinaryOp::MinVecF64x2)"), + ("f64x2.max", "makeBinary(s, BinaryOp::MaxVecF64x2)"), + ("i32x4.trunc_s/f32x4:sat", "makeUnary(s, UnaryOp::TruncSatSVecF32x4ToVecI32x4)"), + ("i32x4.trunc_u/f32x4:sat", "makeUnary(s, UnaryOp::TruncSatUVecF32x4ToVecI32x4)"), + ("i64x2.trunc_s/f64x2:sat", "makeUnary(s, UnaryOp::TruncSatSVecF64x2ToVecI64x2)"), + ("i64x2.trunc_u/f64x2:sat", "makeUnary(s, UnaryOp::TruncSatUVecF64x2ToVecI64x2)"), + ("f32x4.convert_s/i32x4", "makeUnary(s, UnaryOp::ConvertSVecI32x4ToVecF32x4)"), + ("f32x4.convert_u/i32x4", "makeUnary(s, UnaryOp::ConvertUVecI32x4ToVecF32x4)"), + ("f64x2.convert_s/i64x2", "makeUnary(s, UnaryOp::ConvertSVecI64x2ToVecF64x2)"), + ("f64x2.convert_u/i64x2", "makeUnary(s, UnaryOp::ConvertUVecI64x2ToVecF64x2)") ] @@ -308,7 +449,7 @@ class Node: def do_insert(self, full_inst, inst, expr): if inst is "": - assert self.expr is None, "Repeated instruction" + assert self.expr is None, "Repeated instruction " + full_inst self.expr = expr self.inst = full_inst return |