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-rw-r--r--src/binaryen-c.cpp24
-rw-r--r--src/binaryen-c.h8
-rw-r--r--src/ir/ExpressionAnalyzer.cpp8
-rw-r--r--src/ir/ExpressionManipulator.cpp4
-rw-r--r--src/js/binaryen.js-post.js60
-rw-r--r--src/literal.h28
-rw-r--r--src/passes/Print.cpp4
-rw-r--r--src/tools/fuzzing.h28
-rw-r--r--src/wasm-binary.h2
-rw-r--r--src/wasm-builder.h8
-rw-r--r--src/wasm-interpreter.h28
-rw-r--r--src/wasm-stack.h6
-rw-r--r--src/wasm.h4
-rw-r--r--src/wasm/literal.cpp56
-rw-r--r--src/wasm/wasm-binary.cpp34
-rw-r--r--src/wasm/wasm-s-parser.cpp8
-rw-r--r--src/wasm/wasm-validator.cpp8
17 files changed, 159 insertions, 159 deletions
diff --git a/src/binaryen-c.cpp b/src/binaryen-c.cpp
index 6b5481af2..80f8d8276 100644
--- a/src/binaryen-c.cpp
+++ b/src/binaryen-c.cpp
@@ -1027,17 +1027,17 @@ BinaryenExpressionRef BinaryenAtomicWake(BinaryenModuleRef module, BinaryenExpre
return static_cast<Expression*>(ret);
}
-BinaryenExpressionRef BinaryenSIMDExtract(BinaryenModuleRef module, BinaryenOp op, BinaryenExpressionRef vec, uint8_t idx) {
- auto* ret = Builder(*((Module*)module)).makeSIMDExtract(SIMDExtractOp(op), (Expression*) vec, idx);
+BinaryenExpressionRef BinaryenSIMDExtract(BinaryenModuleRef module, BinaryenOp op, BinaryenExpressionRef vec, uint8_t index) {
+ auto* ret = Builder(*((Module*)module)).makeSIMDExtract(SIMDExtractOp(op), (Expression*) vec, index);
if (tracing) {
- traceExpression(ret, "BinaryenSIMDExtract", op, vec, int(idx));
+ traceExpression(ret, "BinaryenSIMDExtract", op, vec, int(index));
}
return static_cast<Expression*>(ret);
}
-BinaryenExpressionRef BinaryenSIMDReplace(BinaryenModuleRef module, BinaryenOp op, BinaryenExpressionRef vec, uint8_t idx, BinaryenExpressionRef value) {
- auto* ret = Builder(*((Module*)module)).makeSIMDReplace(SIMDReplaceOp(op), (Expression*) vec, idx, (Expression*)value);
+BinaryenExpressionRef BinaryenSIMDReplace(BinaryenModuleRef module, BinaryenOp op, BinaryenExpressionRef vec, uint8_t index, BinaryenExpressionRef value) {
+ auto* ret = Builder(*((Module*)module)).makeSIMDReplace(SIMDReplaceOp(op), (Expression*) vec, index, (Expression*)value);
if (tracing) {
- traceExpression(ret, "BinaryenSIMDReplace", op, vec, int(idx), value);
+ traceExpression(ret, "BinaryenSIMDReplace", op, vec, int(index), value);
}
return static_cast<Expression*>(ret);
}
@@ -1843,14 +1843,14 @@ BinaryenExpressionRef BinaryenSIMDExtractGetVec(BinaryenExpressionRef expr) {
assert(expression->is<SIMDExtract>());
return static_cast<SIMDExtract*>(expression)->vec;
}
-uint8_t BinaryenSIMDExtractGetIdx(BinaryenExpressionRef expr) {
+uint8_t BinaryenSIMDExtractGetIndex(BinaryenExpressionRef expr) {
if (tracing) {
- std::cout << " BinaryenSIMDExtractGetIdx(expressions[" << expressions[expr] << "]);\n";
+ std::cout << " BinaryenSIMDExtractGetIndex(expressions[" << expressions[expr] << "]);\n";
}
auto* expression = (Expression*)expr;
assert(expression->is<SIMDExtract>());
- return static_cast<SIMDExtract*>(expression)->idx;
+ return static_cast<SIMDExtract*>(expression)->index;
}
// SIMDReplace
BinaryenOp BinaryenSIMDReplaceGetOp(BinaryenExpressionRef expr) {
@@ -1871,14 +1871,14 @@ BinaryenExpressionRef BinaryenSIMDReplaceGetVec(BinaryenExpressionRef expr) {
assert(expression->is<SIMDReplace>());
return static_cast<SIMDReplace*>(expression)->vec;
}
-uint8_t BinaryenSIMDReplaceGetIdx(BinaryenExpressionRef expr) {
+uint8_t BinaryenSIMDReplaceGetIndex(BinaryenExpressionRef expr) {
if (tracing) {
- std::cout << " BinaryenSIMDReplaceGetIdx(expressions[" << expressions[expr] << "]);\n";
+ std::cout << " BinaryenSIMDReplaceGetIndex(expressions[" << expressions[expr] << "]);\n";
}
auto* expression = (Expression*)expr;
assert(expression->is<SIMDReplace>());
- return static_cast<SIMDReplace*>(expression)->idx;
+ return static_cast<SIMDReplace*>(expression)->index;
}
BinaryenExpressionRef BinaryenSIMDReplaceGetValue(BinaryenExpressionRef expr) {
if (tracing) {
diff --git a/src/binaryen-c.h b/src/binaryen-c.h
index 9d1992851..2a3254f7b 100644
--- a/src/binaryen-c.h
+++ b/src/binaryen-c.h
@@ -535,8 +535,8 @@ BinaryenExpressionRef BinaryenAtomicRMW(BinaryenModuleRef module, BinaryenOp op,
BinaryenExpressionRef BinaryenAtomicCmpxchg(BinaryenModuleRef module, BinaryenIndex bytes, BinaryenIndex offset, BinaryenExpressionRef ptr, BinaryenExpressionRef expected, BinaryenExpressionRef replacement, BinaryenType type);
BinaryenExpressionRef BinaryenAtomicWait(BinaryenModuleRef module, BinaryenExpressionRef ptr, BinaryenExpressionRef expected, BinaryenExpressionRef timeout, BinaryenType type);
BinaryenExpressionRef BinaryenAtomicWake(BinaryenModuleRef module, BinaryenExpressionRef ptr, BinaryenExpressionRef wakeCount);
-BinaryenExpressionRef BinaryenSIMDExtract(BinaryenModuleRef module, BinaryenOp op, BinaryenExpressionRef vec, uint8_t idx);
-BinaryenExpressionRef BinaryenSIMDReplace(BinaryenModuleRef module, BinaryenOp op, BinaryenExpressionRef vec, uint8_t idx, BinaryenExpressionRef value);
+BinaryenExpressionRef BinaryenSIMDExtract(BinaryenModuleRef module, BinaryenOp op, BinaryenExpressionRef vec, uint8_t index);
+BinaryenExpressionRef BinaryenSIMDReplace(BinaryenModuleRef module, BinaryenOp op, BinaryenExpressionRef vec, uint8_t index, BinaryenExpressionRef value);
BinaryenExpressionRef BinaryenSIMDShuffle(BinaryenModuleRef module, BinaryenExpressionRef left, BinaryenExpressionRef right, const uint8_t mask[16]);
BinaryenExpressionRef BinaryenSIMDBitselect(BinaryenModuleRef module, BinaryenExpressionRef left, BinaryenExpressionRef right, BinaryenExpressionRef cond);
BinaryenExpressionRef BinaryenSIMDShift(BinaryenModuleRef module, BinaryenOp op, BinaryenExpressionRef vec, BinaryenExpressionRef shift);
@@ -648,11 +648,11 @@ BinaryenExpressionRef BinaryenAtomicWakeGetWakeCount(BinaryenExpressionRef expr)
BinaryenOp BinaryenSIMDExtractGetOp(BinaryenExpressionRef expr);
BinaryenExpressionRef BinaryenSIMDExtractGetVec(BinaryenExpressionRef expr);
-uint8_t BinaryenSIMDExtractGetIdx(BinaryenExpressionRef expr);
+uint8_t BinaryenSIMDExtractGetIndex(BinaryenExpressionRef expr);
BinaryenOp BinaryenSIMDReplaceGetOp(BinaryenExpressionRef expr);
BinaryenExpressionRef BinaryenSIMDReplaceGetVec(BinaryenExpressionRef expr);
-uint8_t BinaryenSIMDReplaceGetIdx(BinaryenExpressionRef expr);
+uint8_t BinaryenSIMDReplaceGetIndex(BinaryenExpressionRef expr);
BinaryenExpressionRef BinaryenSIMDReplaceGetValue(BinaryenExpressionRef expr);
BinaryenExpressionRef BinaryenSIMDShuffleGetLeft(BinaryenExpressionRef expr);
diff --git a/src/ir/ExpressionAnalyzer.cpp b/src/ir/ExpressionAnalyzer.cpp
index 6b553c909..6ecfb5517 100644
--- a/src/ir/ExpressionAnalyzer.cpp
+++ b/src/ir/ExpressionAnalyzer.cpp
@@ -251,13 +251,13 @@ bool ExpressionAnalyzer::flexibleEqual(Expression* left, Expression* right, Expr
}
case Expression::Id::SIMDExtractId: {
CHECK(SIMDExtract, op);
- CHECK(SIMDExtract, idx);
+ CHECK(SIMDExtract, index);
PUSH(SIMDExtract, vec);
break;
}
case Expression::Id::SIMDReplaceId: {
CHECK(SIMDReplace, op);
- CHECK(SIMDReplace, idx);
+ CHECK(SIMDReplace, index);
PUSH(SIMDReplace, vec);
PUSH(SIMDReplace, value);
break;
@@ -530,13 +530,13 @@ HashType ExpressionAnalyzer::hash(Expression* curr) {
}
case Expression::Id::SIMDExtractId: {
HASH(SIMDExtract, op);
- HASH(SIMDExtract, idx);
+ HASH(SIMDExtract, index);
PUSH(SIMDExtract, vec);
break;
}
case Expression::Id::SIMDReplaceId: {
HASH(SIMDReplace, op);
- HASH(SIMDReplace, idx);
+ HASH(SIMDReplace, index);
PUSH(SIMDReplace, vec);
PUSH(SIMDReplace, value);
break;
diff --git a/src/ir/ExpressionManipulator.cpp b/src/ir/ExpressionManipulator.cpp
index 3f53bccdd..700f7fdb8 100644
--- a/src/ir/ExpressionManipulator.cpp
+++ b/src/ir/ExpressionManipulator.cpp
@@ -115,10 +115,10 @@ Expression* flexibleCopy(Expression* original, Module& wasm, CustomCopier custom
return builder.makeAtomicWake(copy(curr->ptr), copy(curr->wakeCount), curr->offset);
}
Expression* visitSIMDExtract(SIMDExtract* curr) {
- return builder.makeSIMDExtract(curr->op, copy(curr->vec), curr->idx);
+ return builder.makeSIMDExtract(curr->op, copy(curr->vec), curr->index);
}
Expression* visitSIMDReplace(SIMDReplace* curr) {
- return builder.makeSIMDReplace(curr->op, copy(curr->vec), curr->idx, copy(curr->value));
+ return builder.makeSIMDReplace(curr->op, copy(curr->vec), curr->index, copy(curr->value));
}
Expression* visitSIMDShuffle(SIMDShuffle* curr) {
return builder.makeSIMDShuffle(copy(curr->left), copy(curr->right), curr->mask);
diff --git a/src/js/binaryen.js-post.js b/src/js/binaryen.js-post.js
index 11f721d54..dadc94bd7 100644
--- a/src/js/binaryen.js-post.js
+++ b/src/js/binaryen.js-post.js
@@ -1245,14 +1245,14 @@ function wrapModule(module, self) {
'splat': function(value) {
return Module['_BinaryenUnary'](module, Module['SplatVecI8x16'], value);
},
- 'extract_lane_s': function(vec, idx) {
- return Module['_BinaryenSIMDExtract'](module, Module['ExtractLaneSVecI8x16'], vec, idx);
+ 'extract_lane_s': function(vec, index) {
+ return Module['_BinaryenSIMDExtract'](module, Module['ExtractLaneSVecI8x16'], vec, index);
},
- 'extract_lane_u': function(vec, idx) {
- return Module['_BinaryenSIMDExtract'](module, Module['ExtractLaneUVecI8x16'], vec, idx);
+ 'extract_lane_u': function(vec, index) {
+ return Module['_BinaryenSIMDExtract'](module, Module['ExtractLaneUVecI8x16'], vec, index);
},
- 'replace_lane': function(vec, idx, value) {
- return Module['_BinaryenSIMDReplace'](module, Module['ReplaceLaneVecI8x16'], vec, idx, value);
+ 'replace_lane': function(vec, index, value) {
+ return Module['_BinaryenSIMDReplace'](module, Module['ReplaceLaneVecI8x16'], vec, index, value);
},
'eq': function(left, right) {
return Module['_BinaryenBinary'](module, Module['EqVecI8x16'], left, right);
@@ -1329,14 +1329,14 @@ function wrapModule(module, self) {
'splat': function(value) {
return Module['_BinaryenUnary'](module, Module['SplatVecI16x8'], value);
},
- 'extract_lane_s': function(vec, idx) {
- return Module['_BinaryenSIMDExtract'](module, Module['ExtractLaneSVecI16x8'], vec, idx);
+ 'extract_lane_s': function(vec, index) {
+ return Module['_BinaryenSIMDExtract'](module, Module['ExtractLaneSVecI16x8'], vec, index);
},
- 'extract_lane_u': function(vec, idx) {
- return Module['_BinaryenSIMDExtract'](module, Module['ExtractLaneUVecI16x8'], vec, idx);
+ 'extract_lane_u': function(vec, index) {
+ return Module['_BinaryenSIMDExtract'](module, Module['ExtractLaneUVecI16x8'], vec, index);
},
- 'replace_lane': function(vec, idx, value) {
- return Module['_BinaryenSIMDReplace'](module, Module['ReplaceLaneVecI16x8'], vec, idx, value);
+ 'replace_lane': function(vec, index, value) {
+ return Module['_BinaryenSIMDReplace'](module, Module['ReplaceLaneVecI16x8'], vec, index, value);
},
'eq': function(left, right) {
return Module['_BinaryenBinary'](module, Module['EqVecI16x8'], left, right);
@@ -1413,11 +1413,11 @@ function wrapModule(module, self) {
'splat': function(value) {
return Module['_BinaryenUnary'](module, Module['SplatVecI32x4'], value);
},
- 'extract_lane': function(vec, idx) {
- return Module['_BinaryenSIMDExtract'](module, Module['ExtractLaneVecI32x4'], vec, idx);
+ 'extract_lane': function(vec, index) {
+ return Module['_BinaryenSIMDExtract'](module, Module['ExtractLaneVecI32x4'], vec, index);
},
- 'replace_lane': function(vec, idx, value) {
- return Module['_BinaryenSIMDReplace'](module, Module['ReplaceLaneVecI32x4'], vec, idx, value);
+ 'replace_lane': function(vec, index, value) {
+ return Module['_BinaryenSIMDReplace'](module, Module['ReplaceLaneVecI32x4'], vec, index, value);
},
'eq': function(left, right) {
return Module['_BinaryenBinary'](module, Module['EqVecI32x4'], left, right);
@@ -1488,11 +1488,11 @@ function wrapModule(module, self) {
'splat': function(value) {
return Module['_BinaryenUnary'](module, Module['SplatVecI64x2'], value);
},
- 'extract_lane': function(vec, idx) {
- return Module['_BinaryenSIMDExtract'](module, Module['ExtractLaneVecI64x2'], vec, idx);
+ 'extract_lane': function(vec, index) {
+ return Module['_BinaryenSIMDExtract'](module, Module['ExtractLaneVecI64x2'], vec, index);
},
- 'replace_lane': function(vec, idx, value) {
- return Module['_BinaryenSIMDReplace'](module, Module['ReplaceLaneVecI64x2'], vec, idx, value);
+ 'replace_lane': function(vec, index, value) {
+ return Module['_BinaryenSIMDReplace'](module, Module['ReplaceLaneVecI64x2'], vec, index, value);
},
'neg': function(value) {
return Module['_BinaryenUnary'](module, Module['NegVecI64x2'], value);
@@ -1530,11 +1530,11 @@ function wrapModule(module, self) {
'splat': function(value) {
return Module['_BinaryenUnary'](module, Module['SplatVecF32x4'], value);
},
- 'extract_lane': function(vec, idx) {
- return Module['_BinaryenSIMDExtract'](module, Module['ExtractLaneVecF32x4'], vec, idx);
+ 'extract_lane': function(vec, index) {
+ return Module['_BinaryenSIMDExtract'](module, Module['ExtractLaneVecF32x4'], vec, index);
},
- 'replace_lane': function(vec, idx, value) {
- return Module['_BinaryenSIMDReplace'](module, Module['ReplaceLaneVecF32x4'], vec, idx, value);
+ 'replace_lane': function(vec, index, value) {
+ return Module['_BinaryenSIMDReplace'](module, Module['ReplaceLaneVecF32x4'], vec, index, value);
},
'eq': function(left, right) {
return Module['_BinaryenBinary'](module, Module['EqVecF32x4'], left, right);
@@ -1593,11 +1593,11 @@ function wrapModule(module, self) {
'splat': function(value) {
return Module['_BinaryenUnary'](module, Module['SplatVecF64x2'], value);
},
- 'extract_lane': function(vec, idx) {
- return Module['_BinaryenSIMDExtract'](module, Module['ExtractLaneVecF64x2'], vec, idx);
+ 'extract_lane': function(vec, index) {
+ return Module['_BinaryenSIMDExtract'](module, Module['ExtractLaneVecF64x2'], vec, index);
},
- 'replace_lane': function(vec, idx, value) {
- return Module['_BinaryenSIMDReplace'](module, Module['ReplaceLaneVecF64x2'], vec, idx, value);
+ 'replace_lane': function(vec, index, value) {
+ return Module['_BinaryenSIMDReplace'](module, Module['ReplaceLaneVecF64x2'], vec, index, value);
},
'eq': function(left, right) {
return Module['_BinaryenBinary'](module, Module['EqVecF64x2'], left, right);
@@ -2154,7 +2154,7 @@ Module['getExpressionInfo'] = function(expr) {
'type': type,
'op': Module['_BinaryenSIMDExtractGetOp'](expr),
'vec': Module['_BinaryenSIMDExtractGetVec'](expr),
- 'idx': Module['_BinaryenSIMDExtractGetIdx'](expr)
+ 'index': Module['_BinaryenSIMDExtractGetIndex'](expr)
};
case Module['SIMDReplaceId']:
return {
@@ -2162,7 +2162,7 @@ Module['getExpressionInfo'] = function(expr) {
'type': type,
'op': Module['_BinaryenSIMDReplaceGetOp'](expr),
'vec': Module['_BinaryenSIMDReplaceGetVec'](expr),
- 'idx': Module['_BinaryenSIMDReplaceGetIdx'](expr),
+ 'index': Module['_BinaryenSIMDReplaceGetIndex'](expr),
'value': Module['_BinaryenSIMDReplaceGetValue'](expr)
};
case Module['SIMDShuffleId']:
diff --git a/src/literal.h b/src/literal.h
index 6cd148b23..0c9f9da96 100644
--- a/src/literal.h
+++ b/src/literal.h
@@ -205,25 +205,25 @@ public:
Literal shuffleV8x16(const Literal& other, const std::array<uint8_t, 16>& mask) const;
Literal splatI8x16() const;
- Literal extractLaneSI8x16(uint8_t idx) const;
- Literal extractLaneUI8x16(uint8_t idx) const;
- Literal replaceLaneI8x16(const Literal& other, uint8_t idx) const;
+ Literal extractLaneSI8x16(uint8_t index) const;
+ Literal extractLaneUI8x16(uint8_t index) const;
+ Literal replaceLaneI8x16(const Literal& other, uint8_t index) const;
Literal splatI16x8() const;
- Literal extractLaneSI16x8(uint8_t idx) const;
- Literal extractLaneUI16x8(uint8_t idx) const;
- Literal replaceLaneI16x8(const Literal& other, uint8_t idx) const;
+ Literal extractLaneSI16x8(uint8_t index) const;
+ Literal extractLaneUI16x8(uint8_t index) const;
+ Literal replaceLaneI16x8(const Literal& other, uint8_t index) const;
Literal splatI32x4() const;
- Literal extractLaneI32x4(uint8_t idx) const;
- Literal replaceLaneI32x4(const Literal& other, uint8_t idx) const;
+ Literal extractLaneI32x4(uint8_t index) const;
+ Literal replaceLaneI32x4(const Literal& other, uint8_t index) const;
Literal splatI64x2() const;
- Literal extractLaneI64x2(uint8_t idx) const;
- Literal replaceLaneI64x2(const Literal& other, uint8_t idx) const;
+ Literal extractLaneI64x2(uint8_t index) const;
+ Literal replaceLaneI64x2(const Literal& other, uint8_t index) const;
Literal splatF32x4() const;
- Literal extractLaneF32x4(uint8_t idx) const;
- Literal replaceLaneF32x4(const Literal& other, uint8_t idx) const;
+ Literal extractLaneF32x4(uint8_t index) const;
+ Literal replaceLaneF32x4(const Literal& other, uint8_t index) const;
Literal splatF64x2() const;
- Literal extractLaneF64x2(uint8_t idx) const;
- Literal replaceLaneF64x2(const Literal& other, uint8_t idx) const;
+ Literal extractLaneF64x2(uint8_t index) const;
+ Literal replaceLaneF64x2(const Literal& other, uint8_t index) const;
Literal eqI8x16(const Literal& other) const;
Literal neI8x16(const Literal& other) const;
Literal ltSI8x16(const Literal& other) const;
diff --git a/src/passes/Print.cpp b/src/passes/Print.cpp
index 64dd0deae..2cfa5092c 100644
--- a/src/passes/Print.cpp
+++ b/src/passes/Print.cpp
@@ -246,7 +246,7 @@ struct PrintExpressionContents : public Visitor<PrintExpressionContents> {
case ExtractLaneVecF32x4: o << "f32x4.extract_lane"; break;
case ExtractLaneVecF64x2: o << "f64x2.extract_lane"; break;
}
- o << " " << int(curr->idx);
+ o << " " << int(curr->index);
}
void visitSIMDReplace(SIMDReplace* curr) {
prepareColor(o);
@@ -258,7 +258,7 @@ struct PrintExpressionContents : public Visitor<PrintExpressionContents> {
case ReplaceLaneVecF32x4: o << "f32x4.replace_lane"; break;
case ReplaceLaneVecF64x2: o << "f64x2.replace_lane"; break;
}
- o << " " << int(curr->idx);
+ o << " " << int(curr->index);
}
void visitSIMDShuffle(SIMDShuffle* curr) {
prepareColor(o);
diff --git a/src/tools/fuzzing.h b/src/tools/fuzzing.h
index 5aec51c88..1a3da7b22 100644
--- a/src/tools/fuzzing.h
+++ b/src/tools/fuzzing.h
@@ -1643,37 +1643,37 @@ private:
case unreachable: WASM_UNREACHABLE();
}
Expression* vec = make(v128);
- uint8_t idx = 0;
+ uint8_t index = 0;
switch (op) {
case ExtractLaneSVecI8x16:
- case ExtractLaneUVecI8x16: idx = upTo(16); break;
+ case ExtractLaneUVecI8x16: index = upTo(16); break;
case ExtractLaneSVecI16x8:
- case ExtractLaneUVecI16x8: idx = upTo(8); break;
+ case ExtractLaneUVecI16x8: index = upTo(8); break;
case ExtractLaneVecI32x4:
- case ExtractLaneVecF32x4: idx = upTo(4); break;
+ case ExtractLaneVecF32x4: index = upTo(4); break;
case ExtractLaneVecI64x2:
- case ExtractLaneVecF64x2: idx = upTo(2); break;
+ case ExtractLaneVecF64x2: index = upTo(2); break;
}
- return builder.makeSIMDExtract(op, vec, idx);
+ return builder.makeSIMDExtract(op, vec, index);
}
Expression* makeSIMDReplace() {
SIMDReplaceOp op = pick(ReplaceLaneVecI8x16, ReplaceLaneVecI16x8, ReplaceLaneVecI32x4,
ReplaceLaneVecI64x2, ReplaceLaneVecF32x4, ReplaceLaneVecF64x2);
Expression* vec = make(v128);
- uint8_t idx;
+ uint8_t index;
Type lane_t;
switch (op) {
- case ReplaceLaneVecI8x16: idx = upTo(16); lane_t = i32; break;
- case ReplaceLaneVecI16x8: idx = upTo(8); lane_t = i32; break;
- case ReplaceLaneVecI32x4: idx = upTo(4); lane_t = i32; break;
- case ReplaceLaneVecI64x2: idx = upTo(2); lane_t = i64; break;
- case ReplaceLaneVecF32x4: idx = upTo(4); lane_t = f32; break;
- case ReplaceLaneVecF64x2: idx = upTo(2); lane_t = f64; break;
+ case ReplaceLaneVecI8x16: index = upTo(16); lane_t = i32; break;
+ case ReplaceLaneVecI16x8: index = upTo(8); lane_t = i32; break;
+ case ReplaceLaneVecI32x4: index = upTo(4); lane_t = i32; break;
+ case ReplaceLaneVecI64x2: index = upTo(2); lane_t = i64; break;
+ case ReplaceLaneVecF32x4: index = upTo(4); lane_t = f32; break;
+ case ReplaceLaneVecF64x2: index = upTo(2); lane_t = f64; break;
default: WASM_UNREACHABLE();
}
Expression* value = make(lane_t);
- return builder.makeSIMDReplace(op, vec, idx, value);
+ return builder.makeSIMDReplace(op, vec, index, value);
}
Expression* makeSIMDShuffle() {
diff --git a/src/wasm-binary.h b/src/wasm-binary.h
index 36c9f2116..998952bde 100644
--- a/src/wasm-binary.h
+++ b/src/wasm-binary.h
@@ -959,7 +959,7 @@ public:
uint16_t getInt16();
uint32_t getInt32();
uint64_t getInt64();
- uint8_t getLaneIdx(size_t lanes);
+ uint8_t getLaneIndex(size_t lanes);
// it is unsafe to return a float directly, due to ABI issues with the signalling bit
Literal getFloat32Literal();
Literal getFloat64Literal();
diff --git a/src/wasm-builder.h b/src/wasm-builder.h
index dccefa144..f182b1df2 100644
--- a/src/wasm-builder.h
+++ b/src/wasm-builder.h
@@ -293,19 +293,19 @@ public:
ret->finalize();
return ret;
}
- SIMDExtract* makeSIMDExtract(SIMDExtractOp op, Expression* vec, uint8_t idx) {
+ SIMDExtract* makeSIMDExtract(SIMDExtractOp op, Expression* vec, uint8_t index) {
auto* ret = allocator.alloc<SIMDExtract>();
ret->op = op;
ret->vec = vec;
- ret->idx = idx;
+ ret->index = index;
ret->finalize();
return ret;
}
- SIMDReplace* makeSIMDReplace(SIMDReplaceOp op, Expression* vec, uint8_t idx, Expression* value) {
+ SIMDReplace* makeSIMDReplace(SIMDReplaceOp op, Expression* vec, uint8_t index, Expression* value) {
auto* ret = allocator.alloc<SIMDReplace>();
ret->op = op;
ret->vec = vec;
- ret->idx = idx;
+ ret->index = index;
ret->value = value;
ret->finalize();
return ret;
diff --git a/src/wasm-interpreter.h b/src/wasm-interpreter.h
index cec5dd983..c5a08cc9b 100644
--- a/src/wasm-interpreter.h
+++ b/src/wasm-interpreter.h
@@ -549,14 +549,14 @@ public:
if (flow.breaking()) return flow;
Literal vec = flow.value;
switch (curr->op) {
- case ExtractLaneSVecI8x16: return vec.extractLaneSI8x16(curr->idx);
- case ExtractLaneUVecI8x16: return vec.extractLaneUI8x16(curr->idx);
- case ExtractLaneSVecI16x8: return vec.extractLaneSI16x8(curr->idx);
- case ExtractLaneUVecI16x8: return vec.extractLaneUI16x8(curr->idx);
- case ExtractLaneVecI32x4: return vec.extractLaneI32x4(curr->idx);
- case ExtractLaneVecI64x2: return vec.extractLaneI64x2(curr->idx);
- case ExtractLaneVecF32x4: return vec.extractLaneF32x4(curr->idx);
- case ExtractLaneVecF64x2: return vec.extractLaneF64x2(curr->idx);
+ case ExtractLaneSVecI8x16: return vec.extractLaneSI8x16(curr->index);
+ case ExtractLaneUVecI8x16: return vec.extractLaneUI8x16(curr->index);
+ case ExtractLaneSVecI16x8: return vec.extractLaneSI16x8(curr->index);
+ case ExtractLaneUVecI16x8: return vec.extractLaneUI16x8(curr->index);
+ case ExtractLaneVecI32x4: return vec.extractLaneI32x4(curr->index);
+ case ExtractLaneVecI64x2: return vec.extractLaneI64x2(curr->index);
+ case ExtractLaneVecF32x4: return vec.extractLaneF32x4(curr->index);
+ case ExtractLaneVecF64x2: return vec.extractLaneF64x2(curr->index);
}
WASM_UNREACHABLE();
}
@@ -569,12 +569,12 @@ public:
if (flow.breaking()) return flow;
Literal value = flow.value;
switch (curr->op) {
- case ReplaceLaneVecI8x16: return vec.replaceLaneI8x16(value, curr->idx);
- case ReplaceLaneVecI16x8: return vec.replaceLaneI16x8(value, curr->idx);
- case ReplaceLaneVecI32x4: return vec.replaceLaneI32x4(value, curr->idx);
- case ReplaceLaneVecI64x2: return vec.replaceLaneI64x2(value, curr->idx);
- case ReplaceLaneVecF32x4: return vec.replaceLaneF32x4(value, curr->idx);
- case ReplaceLaneVecF64x2: return vec.replaceLaneF64x2(value, curr->idx);
+ case ReplaceLaneVecI8x16: return vec.replaceLaneI8x16(value, curr->index);
+ case ReplaceLaneVecI16x8: return vec.replaceLaneI16x8(value, curr->index);
+ case ReplaceLaneVecI32x4: return vec.replaceLaneI32x4(value, curr->index);
+ case ReplaceLaneVecI64x2: return vec.replaceLaneI64x2(value, curr->index);
+ case ReplaceLaneVecF32x4: return vec.replaceLaneF32x4(value, curr->index);
+ case ReplaceLaneVecF64x2: return vec.replaceLaneF64x2(value, curr->index);
}
WASM_UNREACHABLE();
}
diff --git a/src/wasm-stack.h b/src/wasm-stack.h
index 0c10a88fc..c64fd2759 100644
--- a/src/wasm-stack.h
+++ b/src/wasm-stack.h
@@ -891,7 +891,7 @@ void StackWriter<Mode, Parent>::visitSIMDExtract(SIMDExtract* curr) {
case ExtractLaneVecF32x4: o << U32LEB(BinaryConsts::F32x4ExtractLane); break;
case ExtractLaneVecF64x2: o << U32LEB(BinaryConsts::F64x2ExtractLane); break;
}
- o << uint8_t(curr->idx);
+ o << uint8_t(curr->index);
}
template<StackWriterMode Mode, typename Parent>
@@ -908,8 +908,8 @@ void StackWriter<Mode, Parent>::visitSIMDReplace(SIMDReplace* curr) {
case ReplaceLaneVecF32x4: o << U32LEB(BinaryConsts::F32x4ReplaceLane); break;
case ReplaceLaneVecF64x2: o << U32LEB(BinaryConsts::F64x2ReplaceLane); break;
}
- assert(curr->idx < 16);
- o << uint8_t(curr->idx);
+ assert(curr->index < 16);
+ o << uint8_t(curr->index);
}
template<StackWriterMode Mode, typename Parent>
diff --git a/src/wasm.h b/src/wasm.h
index 52a0ca299..bcdc30dab 100644
--- a/src/wasm.h
+++ b/src/wasm.h
@@ -554,7 +554,7 @@ class SIMDExtract : public SpecificExpression<Expression::SIMDExtractId> {
SIMDExtractOp op;
Expression* vec;
- uint8_t idx;
+ uint8_t index;
void finalize();
};
@@ -566,7 +566,7 @@ class SIMDReplace : public SpecificExpression<Expression::SIMDReplaceId> {
SIMDReplaceOp op;
Expression* vec;
- uint8_t idx;
+ uint8_t index;
Expression* value;
void finalize();
diff --git a/src/wasm/literal.cpp b/src/wasm/literal.cpp
index 8d44b9b73..5f358fa6b 100644
--- a/src/wasm/literal.cpp
+++ b/src/wasm/literal.cpp
@@ -39,13 +39,13 @@ template<typename LaneT, int Lanes>
static void extractBytes(uint8_t (&dest)[16], const LaneArray<Lanes>& lanes) {
std::array<uint8_t, 16> bytes;
const size_t lane_width = 16 / Lanes;
- for (size_t lane_idx = 0; lane_idx < Lanes; ++lane_idx) {
+ for (size_t lane_index = 0; lane_index < Lanes; ++lane_index) {
uint8_t bits[16];
- lanes[lane_idx].getBits(bits);
+ lanes[lane_index].getBits(bits);
LaneT lane;
memcpy(&lane, bits, sizeof(lane));
for (size_t offset = 0; offset < lane_width; ++offset) {
- bytes.at(lane_idx * lane_width + offset) = uint8_t(lane >> (8 * offset));
+ bytes.at(lane_index * lane_width + offset) = uint8_t(lane >> (8 * offset));
}
}
memcpy(&dest, bytes.data(), sizeof(bytes));
@@ -924,12 +924,12 @@ static LaneArray<Lanes> getLanes(const Literal& val) {
const size_t lane_width = 16 / Lanes;
std::array<uint8_t, 16> bytes = val.getv128();
LaneArray<Lanes> lanes;
- for (size_t lane_idx = 0; lane_idx < Lanes; ++lane_idx) {
+ for (size_t lane_index = 0; lane_index < Lanes; ++lane_index) {
LaneT lane(0);
for (size_t offset = 0; offset < lane_width; ++offset) {
- lane |= LaneT(bytes.at(lane_idx * lane_width + offset)) << LaneT(8 * offset);
+ lane |= LaneT(bytes.at(lane_index * lane_width + offset)) << LaneT(8 * offset);
}
- lanes.at(lane_idx) = Literal(lane);
+ lanes.at(lane_index) = Literal(lane);
}
return lanes;
}
@@ -991,40 +991,40 @@ Literal Literal::splatI64x2() const { return splat<Type::i64, 2>(*this); }
Literal Literal::splatF32x4() const { return splat<Type::f32, 4>(*this); }
Literal Literal::splatF64x2() const { return splat<Type::f64, 2>(*this); }
-Literal Literal::extractLaneSI8x16(uint8_t idx) const { return getLanesSI8x16().at(idx); }
-Literal Literal::extractLaneUI8x16(uint8_t idx) const { return getLanesUI8x16().at(idx); }
-Literal Literal::extractLaneSI16x8(uint8_t idx) const { return getLanesSI16x8().at(idx); }
-Literal Literal::extractLaneUI16x8(uint8_t idx) const { return getLanesUI16x8().at(idx); }
-Literal Literal::extractLaneI32x4(uint8_t idx) const { return getLanesI32x4().at(idx); }
-Literal Literal::extractLaneI64x2(uint8_t idx) const { return getLanesI64x2().at(idx); }
-Literal Literal::extractLaneF32x4(uint8_t idx) const { return getLanesF32x4().at(idx); }
-Literal Literal::extractLaneF64x2(uint8_t idx) const { return getLanesF64x2().at(idx); }
+Literal Literal::extractLaneSI8x16(uint8_t index) const { return getLanesSI8x16().at(index); }
+Literal Literal::extractLaneUI8x16(uint8_t index) const { return getLanesUI8x16().at(index); }
+Literal Literal::extractLaneSI16x8(uint8_t index) const { return getLanesSI16x8().at(index); }
+Literal Literal::extractLaneUI16x8(uint8_t index) const { return getLanesUI16x8().at(index); }
+Literal Literal::extractLaneI32x4(uint8_t index) const { return getLanesI32x4().at(index); }
+Literal Literal::extractLaneI64x2(uint8_t index) const { return getLanesI64x2().at(index); }
+Literal Literal::extractLaneF32x4(uint8_t index) const { return getLanesF32x4().at(index); }
+Literal Literal::extractLaneF64x2(uint8_t index) const { return getLanesF64x2().at(index); }
template<int Lanes, LaneArray<Lanes> (Literal::*IntoLanes)() const>
-static Literal replace(const Literal& val, const Literal& other, uint8_t idx) {
+static Literal replace(const Literal& val, const Literal& other, uint8_t index) {
LaneArray<Lanes> lanes = (val.*IntoLanes)();
- lanes.at(idx) = other;
+ lanes.at(index) = other;
auto ret = Literal(lanes);
return ret;
}
-Literal Literal::replaceLaneI8x16(const Literal& other, uint8_t idx) const {
- return replace<16, &Literal::getLanesUI8x16>(*this, other, idx);
+Literal Literal::replaceLaneI8x16(const Literal& other, uint8_t index) const {
+ return replace<16, &Literal::getLanesUI8x16>(*this, other, index);
}
-Literal Literal::replaceLaneI16x8(const Literal& other, uint8_t idx) const {
- return replace<8, &Literal::getLanesUI16x8>(*this, other, idx);
+Literal Literal::replaceLaneI16x8(const Literal& other, uint8_t index) const {
+ return replace<8, &Literal::getLanesUI16x8>(*this, other, index);
}
-Literal Literal::replaceLaneI32x4(const Literal& other, uint8_t idx) const {
- return replace<4, &Literal::getLanesI32x4>(*this, other, idx);
+Literal Literal::replaceLaneI32x4(const Literal& other, uint8_t index) const {
+ return replace<4, &Literal::getLanesI32x4>(*this, other, index);
}
-Literal Literal::replaceLaneI64x2(const Literal& other, uint8_t idx) const {
- return replace<2, &Literal::getLanesI64x2>(*this, other, idx);
+Literal Literal::replaceLaneI64x2(const Literal& other, uint8_t index) const {
+ return replace<2, &Literal::getLanesI64x2>(*this, other, index);
}
-Literal Literal::replaceLaneF32x4(const Literal& other, uint8_t idx) const {
- return replace<4, &Literal::getLanesF32x4>(*this, other, idx);
+Literal Literal::replaceLaneF32x4(const Literal& other, uint8_t index) const {
+ return replace<4, &Literal::getLanesF32x4>(*this, other, index);
}
-Literal Literal::replaceLaneF64x2(const Literal& other, uint8_t idx) const {
- return replace<2, &Literal::getLanesF64x2>(*this, other, idx);
+Literal Literal::replaceLaneF64x2(const Literal& other, uint8_t index) const {
+ return replace<2, &Literal::getLanesF64x2>(*this, other, index);
}
template<int Lanes, LaneArray<Lanes> (Literal::*IntoLanes)() const,
diff --git a/src/wasm/wasm-binary.cpp b/src/wasm/wasm-binary.cpp
index bdd8f327e..de1374444 100644
--- a/src/wasm/wasm-binary.cpp
+++ b/src/wasm/wasm-binary.cpp
@@ -757,11 +757,11 @@ uint64_t WasmBinaryBuilder::getInt64() {
return ret;
}
-uint8_t WasmBinaryBuilder::getLaneIdx(size_t lanes) {
+uint8_t WasmBinaryBuilder::getLaneIndex(size_t lanes) {
if (debug) std::cerr << "<==" << std::endl;
auto ret = getInt8();
if (ret >= lanes) throwError("Illegal lane index");
- if (debug) std::cerr << "getLaneIdx(" << lanes << "): " << ret << " ==>" << std::endl;
+ if (debug) std::cerr << "getLaneIndex(" << lanes << "): " << ret << " ==>" << std::endl;
return ret;
}
@@ -2570,14 +2570,14 @@ bool WasmBinaryBuilder::maybeVisitSIMDStore(Expression*& out, uint32_t code) {
bool WasmBinaryBuilder::maybeVisitSIMDExtract(Expression*& out, uint32_t code) {
SIMDExtract* curr;
switch (code) {
- case BinaryConsts::I8x16ExtractLaneS: curr = allocator.alloc<SIMDExtract>(); curr->op = ExtractLaneSVecI8x16; curr->idx = getLaneIdx(16); break;
- case BinaryConsts::I8x16ExtractLaneU: curr = allocator.alloc<SIMDExtract>(); curr->op = ExtractLaneUVecI8x16; curr->idx = getLaneIdx(16); break;
- case BinaryConsts::I16x8ExtractLaneS: curr = allocator.alloc<SIMDExtract>(); curr->op = ExtractLaneSVecI16x8; curr->idx = getLaneIdx(8); break;
- case BinaryConsts::I16x8ExtractLaneU: curr = allocator.alloc<SIMDExtract>(); curr->op = ExtractLaneUVecI16x8; curr->idx = getLaneIdx(8); break;
- case BinaryConsts::I32x4ExtractLane: curr = allocator.alloc<SIMDExtract>(); curr->op = ExtractLaneVecI32x4; curr->idx = getLaneIdx(4); break;
- case BinaryConsts::I64x2ExtractLane: curr = allocator.alloc<SIMDExtract>(); curr->op = ExtractLaneVecI64x2; curr->idx = getLaneIdx(2); break;
- case BinaryConsts::F32x4ExtractLane: curr = allocator.alloc<SIMDExtract>(); curr->op = ExtractLaneVecF32x4; curr->idx = getLaneIdx(4); break;
- case BinaryConsts::F64x2ExtractLane: curr = allocator.alloc<SIMDExtract>(); curr->op = ExtractLaneVecF64x2; curr->idx = getLaneIdx(2); break;
+ case BinaryConsts::I8x16ExtractLaneS: curr = allocator.alloc<SIMDExtract>(); curr->op = ExtractLaneSVecI8x16; curr->index = getLaneIndex(16); break;
+ case BinaryConsts::I8x16ExtractLaneU: curr = allocator.alloc<SIMDExtract>(); curr->op = ExtractLaneUVecI8x16; curr->index = getLaneIndex(16); break;
+ case BinaryConsts::I16x8ExtractLaneS: curr = allocator.alloc<SIMDExtract>(); curr->op = ExtractLaneSVecI16x8; curr->index = getLaneIndex(8); break;
+ case BinaryConsts::I16x8ExtractLaneU: curr = allocator.alloc<SIMDExtract>(); curr->op = ExtractLaneUVecI16x8; curr->index = getLaneIndex(8); break;
+ case BinaryConsts::I32x4ExtractLane: curr = allocator.alloc<SIMDExtract>(); curr->op = ExtractLaneVecI32x4; curr->index = getLaneIndex(4); break;
+ case BinaryConsts::I64x2ExtractLane: curr = allocator.alloc<SIMDExtract>(); curr->op = ExtractLaneVecI64x2; curr->index = getLaneIndex(2); break;
+ case BinaryConsts::F32x4ExtractLane: curr = allocator.alloc<SIMDExtract>(); curr->op = ExtractLaneVecF32x4; curr->index = getLaneIndex(4); break;
+ case BinaryConsts::F64x2ExtractLane: curr = allocator.alloc<SIMDExtract>(); curr->op = ExtractLaneVecF64x2; curr->index = getLaneIndex(2); break;
default: return false;
}
curr->vec = popNonVoidExpression();
@@ -2589,12 +2589,12 @@ bool WasmBinaryBuilder::maybeVisitSIMDExtract(Expression*& out, uint32_t code) {
bool WasmBinaryBuilder::maybeVisitSIMDReplace(Expression*& out, uint32_t code) {
SIMDReplace* curr;
switch (code) {
- case BinaryConsts::I8x16ReplaceLane: curr = allocator.alloc<SIMDReplace>(); curr->op = ReplaceLaneVecI8x16; curr->idx = getLaneIdx(16); break;
- case BinaryConsts::I16x8ReplaceLane: curr = allocator.alloc<SIMDReplace>(); curr->op = ReplaceLaneVecI16x8; curr->idx = getLaneIdx(8); break;
- case BinaryConsts::I32x4ReplaceLane: curr = allocator.alloc<SIMDReplace>(); curr->op = ReplaceLaneVecI32x4; curr->idx = getLaneIdx(4); break;
- case BinaryConsts::I64x2ReplaceLane: curr = allocator.alloc<SIMDReplace>(); curr->op = ReplaceLaneVecI64x2; curr->idx = getLaneIdx(2); break;
- case BinaryConsts::F32x4ReplaceLane: curr = allocator.alloc<SIMDReplace>(); curr->op = ReplaceLaneVecF32x4; curr->idx = getLaneIdx(4); break;
- case BinaryConsts::F64x2ReplaceLane: curr = allocator.alloc<SIMDReplace>(); curr->op = ReplaceLaneVecF64x2; curr->idx = getLaneIdx(2); break;
+ case BinaryConsts::I8x16ReplaceLane: curr = allocator.alloc<SIMDReplace>(); curr->op = ReplaceLaneVecI8x16; curr->index = getLaneIndex(16); break;
+ case BinaryConsts::I16x8ReplaceLane: curr = allocator.alloc<SIMDReplace>(); curr->op = ReplaceLaneVecI16x8; curr->index = getLaneIndex(8); break;
+ case BinaryConsts::I32x4ReplaceLane: curr = allocator.alloc<SIMDReplace>(); curr->op = ReplaceLaneVecI32x4; curr->index = getLaneIndex(4); break;
+ case BinaryConsts::I64x2ReplaceLane: curr = allocator.alloc<SIMDReplace>(); curr->op = ReplaceLaneVecI64x2; curr->index = getLaneIndex(2); break;
+ case BinaryConsts::F32x4ReplaceLane: curr = allocator.alloc<SIMDReplace>(); curr->op = ReplaceLaneVecF32x4; curr->index = getLaneIndex(4); break;
+ case BinaryConsts::F64x2ReplaceLane: curr = allocator.alloc<SIMDReplace>(); curr->op = ReplaceLaneVecF64x2; curr->index = getLaneIndex(2); break;
default: return false;
}
curr->value = popNonVoidExpression();
@@ -2610,7 +2610,7 @@ bool WasmBinaryBuilder::maybeVisitSIMDShuffle(Expression*& out, uint32_t code) {
}
auto* curr = allocator.alloc<SIMDShuffle>();
for (auto i = 0; i < 16; ++i) {
- curr->mask[i] = getLaneIdx(32);
+ curr->mask[i] = getLaneIndex(32);
}
curr->right = popNonVoidExpression();
curr->left = popNonVoidExpression();
diff --git a/src/wasm/wasm-s-parser.cpp b/src/wasm/wasm-s-parser.cpp
index ac60cb208..43fdb0a5a 100644
--- a/src/wasm/wasm-s-parser.cpp
+++ b/src/wasm/wasm-s-parser.cpp
@@ -1077,7 +1077,7 @@ Expression* SExpressionWasmBuilder::makeAtomicWake(Element& s) {
return ret;
}
-static uint8_t parseLaneIdx(const Element* s, size_t lanes) {
+static uint8_t parseLaneIndex(const Element* s, size_t lanes) {
const char *str = s->c_str();
char *end;
auto n = static_cast<unsigned long long>(strtoll(str, &end, 10));
@@ -1089,7 +1089,7 @@ static uint8_t parseLaneIdx(const Element* s, size_t lanes) {
Expression* SExpressionWasmBuilder::makeSIMDExtract(Element& s, SIMDExtractOp op, size_t lanes) {
auto ret = allocator.alloc<SIMDExtract>();
ret->op = op;
- ret->idx = parseLaneIdx(s[1], lanes);
+ ret->index = parseLaneIndex(s[1], lanes);
ret->vec = parseExpression(s[2]);
ret->finalize();
return ret;
@@ -1098,7 +1098,7 @@ Expression* SExpressionWasmBuilder::makeSIMDExtract(Element& s, SIMDExtractOp op
Expression* SExpressionWasmBuilder::makeSIMDReplace(Element& s, SIMDReplaceOp op, size_t lanes) {
auto ret = allocator.alloc<SIMDReplace>();
ret->op = op;
- ret->idx = parseLaneIdx(s[1], lanes);
+ ret->index = parseLaneIndex(s[1], lanes);
ret->vec = parseExpression(s[2]);
ret->value = parseExpression(s[3]);
ret->finalize();
@@ -1108,7 +1108,7 @@ Expression* SExpressionWasmBuilder::makeSIMDReplace(Element& s, SIMDReplaceOp op
Expression* SExpressionWasmBuilder::makeSIMDShuffle(Element& s) {
auto ret = allocator.alloc<SIMDShuffle>();
for (size_t i = 0; i < 16; ++i) {
- ret->mask[i] = parseLaneIdx(s[i+1], 32);
+ ret->mask[i] = parseLaneIndex(s[i+1], 32);
}
ret->left = parseExpression(s[17]);
ret->right = parseExpression(s[18]);
diff --git a/src/wasm/wasm-validator.cpp b/src/wasm/wasm-validator.cpp
index 7137e0860..ef4d90fbd 100644
--- a/src/wasm/wasm-validator.cpp
+++ b/src/wasm/wasm-validator.cpp
@@ -590,7 +590,7 @@ void FunctionValidator::visitSIMDExtract(SIMDExtract* curr) {
case ExtractLaneVecF64x2: lane_t = f64; lanes = 2; break;
}
shouldBeEqualOrFirstIsUnreachable(curr->type, lane_t, curr, "extract_lane must have same type as vector lane");
- shouldBeTrue(curr->idx < lanes, curr, "invalid lane index");
+ shouldBeTrue(curr->index < lanes, curr, "invalid lane index");
}
void FunctionValidator::visitSIMDReplace(SIMDReplace* curr) {
@@ -608,7 +608,7 @@ void FunctionValidator::visitSIMDReplace(SIMDReplace* curr) {
case ReplaceLaneVecF64x2: lane_t = f64; lanes = 2; break;
}
shouldBeEqualOrFirstIsUnreachable(curr->value->type, lane_t, curr, "unexpected value type");
- shouldBeTrue(curr->idx < lanes, curr, "invalid lane index");
+ shouldBeTrue(curr->index < lanes, curr, "invalid lane index");
}
void FunctionValidator::visitSIMDShuffle(SIMDShuffle* curr) {
@@ -616,8 +616,8 @@ void FunctionValidator::visitSIMDShuffle(SIMDShuffle* curr) {
shouldBeEqualOrFirstIsUnreachable(curr->type, v128, curr, "v128.shuffle must have type v128");
shouldBeEqualOrFirstIsUnreachable(curr->left->type, v128, curr, "expected operand of type v128");
shouldBeEqualOrFirstIsUnreachable(curr->right->type, v128, curr, "expected operand of type v128");
- for (uint8_t idx : curr->mask) {
- shouldBeTrue(idx < 32, curr, "Invalid lane index in mask");
+ for (uint8_t index : curr->mask) {
+ shouldBeTrue(index < 32, curr, "Invalid lane index in mask");
}
}
generated by cgit v1.2.3 (git 2.39.1) at 2025-08-05 17:26:31 +0000