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authorNg Zhi An <ngzhian@gmail.com>2021-03-22 15:22:02 -0700
committerGitHub <noreply@github.com>2021-03-22 15:22:02 -0700
commit2c7d2572414aad39341734d1513a6cd94759a320 (patch)
tree4b71cafd0fbee7c1a4920a96b8d4e11138f7264a /src/opcode.cc
parentc7293e42c587cab2b15eaf2934f574f84eeab9e5 (diff)
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[simd] Implement load lane (#1646)
This is a new kind of ir/ast node/instruction. It has 3 immediates: memarg align, memarg offset, and lane index. This required new visitor functions in all the places. Drive-by cleanup to share the simd lane parsing logic between shuffle, lane op and this new load lane instructions. This requires rebasing some tests because the error messages are slightly different now.
Diffstat (limited to 'src/opcode.cc')
-rw-r--r--src/opcode.cc8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/opcode.cc b/src/opcode.cc
index 1590fc70..174c2675 100644
--- a/src/opcode.cc
+++ b/src/opcode.cc
@@ -306,6 +306,10 @@ bool Opcode::IsEnabled(const Features& features) const {
case Opcode::V128Load16Splat:
case Opcode::V128Load32Splat:
case Opcode::V128Load64Splat:
+ case Opcode::V128Load8Lane:
+ case Opcode::V128Load16Lane:
+ case Opcode::V128Load32Lane:
+ case Opcode::V128Load64Lane:
case Opcode::I8X16Abs:
case Opcode::I16X8Abs:
case Opcode::I32X4Abs:
@@ -346,23 +350,27 @@ uint32_t Opcode::GetSimdLaneCount() const {
case Opcode::I8X16ExtractLaneS:
case Opcode::I8X16ExtractLaneU:
case Opcode::I8X16ReplaceLane:
+ case Opcode::V128Load8Lane:
return 16;
break;
case Opcode::I16X8ExtractLaneS:
case Opcode::I16X8ExtractLaneU:
case Opcode::I16X8ReplaceLane:
+ case Opcode::V128Load16Lane:
return 8;
break;
case Opcode::F32X4ExtractLane:
case Opcode::F32X4ReplaceLane:
case Opcode::I32X4ExtractLane:
case Opcode::I32X4ReplaceLane:
+ case Opcode::V128Load32Lane:
return 4;
break;
case Opcode::F64X2ExtractLane:
case Opcode::F64X2ReplaceLane:
case Opcode::I64X2ExtractLane:
case Opcode::I64X2ReplaceLane:
+ case Opcode::V128Load64Lane:
return 2;
break;
default: