Add Atomic instructions (#633)

This adds support for all atomic instructions, enabled via the
`--enable-threads` flag.

It supports all tools: parsing text, decoding binary, validation, and
interpreting. It does not currently ensure that the memory is marked as
shared; that flag is not supported in wabt yet.

1 files changed, 73 insertions, 6 deletions

diff --git a/src/opcode.cc b/src/opcode.cc
index 3afd61ba..cadb4987 100644
--- a/src/opcode.cc
+++ b/src/opcode.cc
@@ -24,14 +24,17 @@ namespace wabt {
 
 // static
 Opcode::Info Opcode::infos_[] = {
-#define WABT_OPCODE(rtype, type1, type2, mem_size, prefix, code, Name, text) \
-  {text,     Type::rtype, Type::type1, Type::type2,                          \
-   mem_size, prefix,      code,        PrefixCode(prefix, code)},
+#define WABT_OPCODE(rtype, type1, type2, type3, mem_size, prefix, code, Name, \
+                    text)                                                     \
+  {text,        Type::rtype, Type::type1,                                     \
+   Type::type2, Type::type3, mem_size,                                        \
+   prefix,      code,        PrefixCode(prefix, code)},
 #include "src/opcode.def"
 #undef WABT_OPCODE
 };
 
-#define WABT_OPCODE(rtype, type1, type2, mem_size, prefix, code, Name, text) \
+#define WABT_OPCODE(rtype, type1, type2, type3, mem_size, prefix, code, Name, \
+                    text)                                                     \
   /* static */ Opcode Opcode::Name##_Opcode(Opcode::Name);
 #include "src/opcode.def"
 #undef WABT_OPCODE
@@ -66,8 +69,9 @@ Opcode::Info Opcode::GetInfo() const {
   uint32_t code;
   DecodeInvalidOpcode(enum_, &prefix, &code);
   const Info invalid_info = {
-      "<invalid>", Type::Void, Type::Void, Type::Void,
-      0,           prefix,     code,       PrefixCode(prefix, code),
+      "<invalid>", Type::Void, Type::Void,
+      Type::Void,  Type::Void, 0,
+      prefix,      code,       PrefixCode(prefix, code),
   };
   return invalid_info;
 }
@@ -107,6 +111,69 @@ bool Opcode::IsEnabled(const Features& features) const {
     case Opcode::I64Extend8S:
     case Opcode::I64Extend16S:
     case Opcode::I64Extend32S:
+    case Opcode::I32AtomicLoad:
+    case Opcode::I64AtomicLoad:
+    case Opcode::I32AtomicLoad8U:
+    case Opcode::I32AtomicLoad16U:
+    case Opcode::I64AtomicLoad8U:
+    case Opcode::I64AtomicLoad16U:
+    case Opcode::I64AtomicLoad32U:
+    case Opcode::I32AtomicStore:
+    case Opcode::I64AtomicStore:
+    case Opcode::I32AtomicStore8:
+    case Opcode::I32AtomicStore16:
+    case Opcode::I64AtomicStore8:
+    case Opcode::I64AtomicStore16:
+    case Opcode::I64AtomicStore32:
+    case Opcode::I32AtomicRmwAdd:
+    case Opcode::I64AtomicRmwAdd:
+    case Opcode::I32AtomicRmw8UAdd:
+    case Opcode::I32AtomicRmw16UAdd:
+    case Opcode::I64AtomicRmw8UAdd:
+    case Opcode::I64AtomicRmw16UAdd:
+    case Opcode::I64AtomicRmw32UAdd:
+    case Opcode::I32AtomicRmwSub:
+    case Opcode::I64AtomicRmwSub:
+    case Opcode::I32AtomicRmw8USub:
+    case Opcode::I32AtomicRmw16USub:
+    case Opcode::I64AtomicRmw8USub:
+    case Opcode::I64AtomicRmw16USub:
+    case Opcode::I64AtomicRmw32USub:
+    case Opcode::I32AtomicRmwAnd:
+    case Opcode::I64AtomicRmwAnd:
+    case Opcode::I32AtomicRmw8UAnd:
+    case Opcode::I32AtomicRmw16UAnd:
+    case Opcode::I64AtomicRmw8UAnd:
+    case Opcode::I64AtomicRmw16UAnd:
+    case Opcode::I64AtomicRmw32UAnd:
+    case Opcode::I32AtomicRmwOr:
+    case Opcode::I64AtomicRmwOr:
+    case Opcode::I32AtomicRmw8UOr:
+    case Opcode::I32AtomicRmw16UOr:
+    case Opcode::I64AtomicRmw8UOr:
+    case Opcode::I64AtomicRmw16UOr:
+    case Opcode::I64AtomicRmw32UOr:
+    case Opcode::I32AtomicRmwXor:
+    case Opcode::I64AtomicRmwXor:
+    case Opcode::I32AtomicRmw8UXor:
+    case Opcode::I32AtomicRmw16UXor:
+    case Opcode::I64AtomicRmw8UXor:
+    case Opcode::I64AtomicRmw16UXor:
+    case Opcode::I64AtomicRmw32UXor:
+    case Opcode::I32AtomicRmwXchg:
+    case Opcode::I64AtomicRmwXchg:
+    case Opcode::I32AtomicRmw8UXchg:
+    case Opcode::I32AtomicRmw16UXchg:
+    case Opcode::I64AtomicRmw8UXchg:
+    case Opcode::I64AtomicRmw16UXchg:
+    case Opcode::I64AtomicRmw32UXchg:
+    case Opcode::I32AtomicRmwCmpxchg:
+    case Opcode::I64AtomicRmwCmpxchg:
+    case Opcode::I32AtomicRmw8UCmpxchg:
+    case Opcode::I32AtomicRmw16UCmpxchg:
+    case Opcode::I64AtomicRmw8UCmpxchg:
+    case Opcode::I64AtomicRmw16UCmpxchg:
+    case Opcode::I64AtomicRmw32UCmpxchg:
       return features.threads_enabled();
 
     // Interpreter opcodes are never "enabled".