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| author | Keith Winstein <208955+keithw@users.noreply.github.com> | 2024-12-17 19:06:57 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-12-17 19:06:57 -0800 |
| commit | ea193b40d6d4a1a697d68ae855b2b3b3e263b377 (patch) | |
| tree | 03e10d23cf9883f08657f69fa50c66a516ebe17f /src/prebuilt/wasm2c_simd_source_declarations.cc | |
| parent | 4e7d7efe6e9a786370848e669041bdc237730a8b (diff) | |
| download | wabt-main.tar.gz wabt-main.tar.bz2 wabt-main.zip | |
wasm2c: harmonize bulk mem ops re: i32/i64 (#2506) + parametrize memchecks per-memory (#2507)HEADmain
The PR updates the bulk memory operations (memory.fill, memory.copy,
table.fill, etc.) to support 64-bit addresses and counts. Previously these functions
only took u32's, even with memory64 enabled. (#2506)
This PR also allows "software-bounds-checked" memories and "guard-page-checked"
memories to coexist in the same module. It creates two versions of every memory
operation: an unrestricted version (that works with any memory) and a _default32
version (for memories with default page size and i32 indexing). (#2507)
#2506 and #2507 have been squashed together to avoid a performance regression.
This is a stepping stone to supporting custom-page-sizes (which will need to be
software-bounds-checked) (#2508).
Diffstat (limited to 'src/prebuilt/wasm2c_simd_source_declarations.cc')
| -rw-r--r-- | src/prebuilt/wasm2c_simd_source_declarations.cc | 46 |
1 files changed, 26 insertions, 20 deletions
diff --git a/src/prebuilt/wasm2c_simd_source_declarations.cc b/src/prebuilt/wasm2c_simd_source_declarations.cc index 5b903b26..a43a0006 100644 --- a/src/prebuilt/wasm2c_simd_source_declarations.cc +++ b/src/prebuilt/wasm2c_simd_source_declarations.cc @@ -15,26 +15,26 @@ R"w2c_template(#endif R"w2c_template(// TODO: equivalent constraint for ARM and other architectures )w2c_template" R"w2c_template( -#define DEFINE_SIMD_LOAD_FUNC(name, func, t) \ +#define DEFINE_SIMD_LOAD_FUNC(name, func, t) \ )w2c_template" -R"w2c_template( static inline v128 name(wasm_rt_memory_t* mem, u64 addr) { \ +R"w2c_template( static inline v128 name##_unchecked(wasm_rt_memory_t* mem, u64 addr) { \ )w2c_template" -R"w2c_template( MEMCHECK(mem, addr, t); \ +R"w2c_template( v128 result = func(MEM_ADDR(mem, addr, sizeof(t))); \ )w2c_template" -R"w2c_template( v128 result = func(MEM_ADDR(mem, addr, sizeof(t))); \ +R"w2c_template( SIMD_FORCE_READ(result); \ )w2c_template" -R"w2c_template( SIMD_FORCE_READ(result); \ +R"w2c_template( return result; \ )w2c_template" -R"w2c_template( return result; \ +R"w2c_template( } \ )w2c_template" -R"w2c_template( } +R"w2c_template( DEF_MEM_CHECKS0(name, _, t, return, v128); )w2c_template" R"w2c_template( #define DEFINE_SIMD_LOAD_LANE(name, func, t, lane) \ )w2c_template" -R"w2c_template( static inline v128 name(wasm_rt_memory_t* mem, u64 addr, v128 vec) { \ +R"w2c_template( static inline v128 name##_unchecked(wasm_rt_memory_t* mem, u64 addr, \ )w2c_template" -R"w2c_template( MEMCHECK(mem, addr, t); \ +R"w2c_template( v128 vec) { \ )w2c_template" R"w2c_template( v128 result = func(MEM_ADDR(mem, addr, sizeof(t)), vec, lane); \ )w2c_template" @@ -42,29 +42,35 @@ R"w2c_template( SIMD_FORCE_READ(result); )w2c_template" R"w2c_template( return result; \ )w2c_template" -R"w2c_template( } +R"w2c_template( } \ +)w2c_template" +R"w2c_template( DEF_MEM_CHECKS1(name, _, t, return, v128, v128); )w2c_template" R"w2c_template( -#define DEFINE_SIMD_STORE(name, t) \ +#define DEFINE_SIMD_STORE(name, t) \ +)w2c_template" +R"w2c_template( static inline void name##_unchecked(wasm_rt_memory_t* mem, u64 addr, \ )w2c_template" -R"w2c_template( static inline void name(wasm_rt_memory_t* mem, u64 addr, v128 value) { \ +R"w2c_template( v128 value) { \ )w2c_template" -R"w2c_template( MEMCHECK(mem, addr, t); \ +R"w2c_template( simde_wasm_v128_store(MEM_ADDR(mem, addr, sizeof(t)), value); \ )w2c_template" -R"w2c_template( simde_wasm_v128_store(MEM_ADDR(mem, addr, sizeof(t)), value); \ +R"w2c_template( } \ )w2c_template" -R"w2c_template( } +R"w2c_template( DEF_MEM_CHECKS1(name, _, t, , void, v128); )w2c_template" R"w2c_template( -#define DEFINE_SIMD_STORE_LANE(name, func, t, lane) \ +#define DEFINE_SIMD_STORE_LANE(name, func, t, lane) \ +)w2c_template" +R"w2c_template( static inline void name##_unchecked(wasm_rt_memory_t* mem, u64 addr, \ )w2c_template" -R"w2c_template( static inline void name(wasm_rt_memory_t* mem, u64 addr, v128 value) { \ +R"w2c_template( v128 value) { \ )w2c_template" -R"w2c_template( MEMCHECK(mem, addr, t); \ +R"w2c_template( func(MEM_ADDR(mem, addr, sizeof(t)), value, lane); \ )w2c_template" -R"w2c_template( func(MEM_ADDR(mem, addr, sizeof(t)), value, lane); \ +R"w2c_template( } \ )w2c_template" -R"w2c_template( } +R"w2c_template( DEF_MEM_CHECKS1(name, _, t, , void, v128); )w2c_template" R"w2c_template( // clang-format off |