[simd] Implement load lane (#1646)

This is a new kind of ir/ast node/instruction. It has 3 immediates:
memarg align, memarg offset, and lane index. This required new visitor
functions in all the places.

Drive-by cleanup to share the simd lane parsing logic between shuffle,
lane op and this new load lane instructions. This requires rebasing some
tests because the error messages are slightly different now.

1 files changed, 14 insertions, 0 deletions

diff --git a/src/wat-writer.cc b/src/wat-writer.cc
index d6daa584..f23673e6 100644
--- a/src/wat-writer.cc
+++ b/src/wat-writer.cc
@@ -572,6 +572,7 @@ class WatWriter::ExprVisitorDelegate : public ExprVisitor::Delegate {
   Result OnAtomicRmwCmpxchgExpr(AtomicRmwCmpxchgExpr*) override;
   Result OnTernaryExpr(TernaryExpr*) override;
   Result OnSimdLaneOpExpr(SimdLaneOpExpr*) override;
+  Result OnSimdLoadLaneExpr(SimdLoadLaneExpr*) override;
   Result OnSimdShuffleOpExpr(SimdShuffleOpExpr*) override;
   Result OnLoadSplatExpr(LoadSplatExpr*) override;
   Result OnLoadZeroExpr(LoadZeroExpr*) override;
@@ -976,6 +977,19 @@ Result WatWriter::ExprVisitorDelegate::OnSimdLaneOpExpr(SimdLaneOpExpr* expr) {
   return Result::Ok;
 }
 
+Result WatWriter::ExprVisitorDelegate::OnSimdLoadLaneExpr(SimdLoadLaneExpr* expr) {
+  writer_->WritePutsSpace(expr->opcode.GetName());
+  if (expr->offset) {
+    writer_->Writef("offset=%" PRIaddress, expr->offset);
+  }
+  if (!expr->opcode.IsNaturallyAligned(expr->align)) {
+    writer_->Writef("align=%" PRIaddress, expr->align);
+  }
+  writer_->Writef("%" PRIu64, (expr->val));
+  writer_->WriteNewline(NO_FORCE_NEWLINE);
+  return Result::Ok;
+}
+
 Result WatWriter::ExprVisitorDelegate::OnSimdShuffleOpExpr(
     SimdShuffleOpExpr* expr) {
   writer_->WritePutsSpace(expr->opcode.GetName());