summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
Diffstat (limited to 'src')
-rw-r--r--src/c-writer.cc29
1 files changed, 29 insertions, 0 deletions
diff --git a/src/c-writer.cc b/src/c-writer.cc
index d1129b20..db3f8a43 100644
--- a/src/c-writer.cc
+++ b/src/c-writer.cc
@@ -264,8 +264,11 @@ class CWriter {
void Write(const UnaryExpr&);
void Write(const TernaryExpr&);
void Write(const SimdLaneOpExpr&);
+ void Write(const SimdLoadLaneExpr&);
+ void Write(const SimdStoreLaneExpr&);
void Write(const SimdShuffleOpExpr&);
void Write(const LoadSplatExpr&);
+ void Write(const LoadZeroExpr&);
const WriteCOptions& options_;
const Module* module_ = nullptr;
@@ -1572,6 +1575,16 @@ void CWriter::Write(const ExprList& exprs) {
break;
}
+ case ExprType::SimdLoadLane: {
+ Write(*cast<SimdLoadLaneExpr>(&expr));
+ break;
+ }
+
+ case ExprType::SimdStoreLane: {
+ Write(*cast<SimdStoreLaneExpr>(&expr));
+ break;
+ }
+
case ExprType::SimdShuffleOp: {
Write(*cast<SimdShuffleOpExpr>(&expr));
break;
@@ -1581,6 +1594,10 @@ void CWriter::Write(const ExprList& exprs) {
Write(*cast<LoadSplatExpr>(&expr));
break;
+ case ExprType::LoadZero:
+ Write(*cast<LoadZeroExpr>(&expr));
+ break;
+
case ExprType::Unreachable:
Write("UNREACHABLE;", Newline());
return;
@@ -2171,6 +2188,14 @@ void CWriter::Write(const SimdLaneOpExpr& expr) {
PushType(result_type);
}
+void CWriter::Write(const SimdLoadLaneExpr& expr) {
+ UNIMPLEMENTED("SIMD support");
+}
+
+void CWriter::Write(const SimdStoreLaneExpr& expr) {
+ UNIMPLEMENTED("SIMD support");
+}
+
void CWriter::Write(const SimdShuffleOpExpr& expr) {
Type result_type = expr.opcode.GetResultType();
Write(StackVar(1, result_type), " = ", expr.opcode.GetName(), "(",
@@ -2195,6 +2220,10 @@ void CWriter::Write(const LoadSplatExpr& expr) {
PushType(result_type);
}
+void CWriter::Write(const LoadZeroExpr& expr) {
+ UNIMPLEMENTED("SIMD support");
+}
+
void CWriter::WriteCHeader() {
stream_ = h_stream_;
std::string guard = GenerateHeaderGuard();