| Commit message (Collapse) | Author | Age | Files | Lines |
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* SIMD is now phase 5, enable it by default
* Update test flags, rebase test, and docs
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* Update v128.const WAT parsing to conform to the SIMD draft
* manually fix indentation
* rename no_lanes to lane_count
* Fix parsing of OOB integers
* Update simd shuffle tests to new syntax
* Add the v128.const type tokens to the lexer.
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The lane-wise SIMD relational operators where setting false lanes to zero and
true lanes to 1, but according to the spec these operators clear all bits of
false lanes, and set all bits of true ones.
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Including:
i8x16.ge_s, i8x16_ge_u
i16x8.ge_s, i16x8_ge_u
i32x4.ge_s, i32x4_ge_u
f32x4.ge
f64x2.ge
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Including:
i8x16.gt_s, i8x16_gt_u
i16x8.gt_s, i16x8_gt_u
i32x4.gt_s, i32x4_gt_u
f32x4.gt
f64x2.gt
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Including:
i8x16.le_s, i8x16_le_u
i16x8.le_s, i16x8_le_u
i32x4.le_s, i32x4_le_u
f32x4.le
f64x2.le
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Including:
i8x16.lt_s, i8x16_lt_u
i16x8.lt_s, i16x8_lt_u
i32x4.lt_s, i32x4_lt_u
f32x4.lt
f64x2.lt
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Including:
(i8x16/i16x8/i32x4/f32x4/f64x2).ne
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Including:
(i8x16/i16x8/i32x4/f32x4/f64x2).eq
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