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| author | Brendan Dahl <brendan.dahl@gmail.com> | 2024-08-08 10:22:51 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-08-08 10:22:51 -0700 |
| commit | d945aa489a1ad62c130e04ceea8492c7a728ab57 (patch) | |
| tree | 04e529f11ed8b2dfe9d98f84d25f7bef05f158b0 /scripts/gen-s-parser.py | |
| parent | c9fd92c25a74a70c9730f1b39b49ef3d91a1a7f1 (diff) | |
| download | binaryen-d945aa489a1ad62c130e04ceea8492c7a728ab57.tar.gz binaryen-d945aa489a1ad62c130e04ceea8492c7a728ab57.tar.bz2 binaryen-d945aa489a1ad62c130e04ceea8492c7a728ab57.zip | |
[FP16] Implement lane access instructions. (#6821)
Specified at
https://github.com/WebAssembly/half-precision/blob/main/proposals/half-precision/Overview.md
Diffstat (limited to 'scripts/gen-s-parser.py')
| -rwxr-xr-x | scripts/gen-s-parser.py | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/scripts/gen-s-parser.py b/scripts/gen-s-parser.py index f35109644..9519ad4ee 100755 --- a/scripts/gen-s-parser.py +++ b/scripts/gen-s-parser.py @@ -298,6 +298,9 @@ instructions = [ ("i64x2.splat", "makeUnary(UnaryOp::SplatVecI64x2)"), ("i64x2.extract_lane", "makeSIMDExtract(SIMDExtractOp::ExtractLaneVecI64x2, 2)"), ("i64x2.replace_lane", "makeSIMDReplace(SIMDReplaceOp::ReplaceLaneVecI64x2, 2)"), + ("f16x8.splat", "makeUnary(UnaryOp::SplatVecF16x8)"), + ("f16x8.extract_lane", "makeSIMDExtract(SIMDExtractOp::ExtractLaneVecF16x8, 8)"), + ("f16x8.replace_lane", "makeSIMDReplace(SIMDReplaceOp::ReplaceLaneVecF16x8, 8)"), ("f32x4.splat", "makeUnary(UnaryOp::SplatVecF32x4)"), ("f32x4.extract_lane", "makeSIMDExtract(SIMDExtractOp::ExtractLaneVecF32x4, 4)"), ("f32x4.replace_lane", "makeSIMDReplace(SIMDReplaceOp::ReplaceLaneVecF32x4, 4)"), |