diff options
| author | Brendan Dahl <brendan.dahl@gmail.com> | 2024-08-27 13:07:49 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-08-27 13:07:49 -0700 |
| commit | e2ceaa58c10e9ee3e9eece42466243f5a8aff125 (patch) | |
| tree | 3815a50a2394632b1dab7bf83e737f828771e76f /scripts | |
| parent | 52118e536238c10f6873390a6ca475a44350bc71 (diff) | |
| download | binaryen-e2ceaa58c10e9ee3e9eece42466243f5a8aff125.tar.gz binaryen-e2ceaa58c10e9ee3e9eece42466243f5a8aff125.tar.bz2 binaryen-e2ceaa58c10e9ee3e9eece42466243f5a8aff125.zip | |
Rename relaxed SIMD fma instructions to match spec. (#6876)
The instructions relaxed_fma and relaxed_fnma have been renamed to
relaxed_madd and relaxed_nmadd.
https://github.com/WebAssembly/relaxed-simd/blob/main/proposals/relaxed-simd/Overview.md#binary-format
Diffstat (limited to 'scripts')
| -rwxr-xr-x | scripts/gen-s-parser.py | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/scripts/gen-s-parser.py b/scripts/gen-s-parser.py index 49fa6afb6..0b5703b9e 100755 --- a/scripts/gen-s-parser.py +++ b/scripts/gen-s-parser.py @@ -547,10 +547,10 @@ instructions = [ ("i32x4.relaxed_trunc_f32x4_u", "makeUnary(UnaryOp::RelaxedTruncUVecF32x4ToVecI32x4)"), ("i32x4.relaxed_trunc_f64x2_s_zero", "makeUnary(UnaryOp::RelaxedTruncZeroSVecF64x2ToVecI32x4)"), ("i32x4.relaxed_trunc_f64x2_u_zero", "makeUnary(UnaryOp::RelaxedTruncZeroUVecF64x2ToVecI32x4)"), - ("f32x4.relaxed_fma", "makeSIMDTernary(SIMDTernaryOp::RelaxedFmaVecF32x4)"), - ("f32x4.relaxed_fms", "makeSIMDTernary(SIMDTernaryOp::RelaxedFmsVecF32x4)"), - ("f64x2.relaxed_fma", "makeSIMDTernary(SIMDTernaryOp::RelaxedFmaVecF64x2)"), - ("f64x2.relaxed_fms", "makeSIMDTernary(SIMDTernaryOp::RelaxedFmsVecF64x2)"), + ("f32x4.relaxed_madd", "makeSIMDTernary(SIMDTernaryOp::RelaxedMaddVecF32x4)"), + ("f32x4.relaxed_nmadd", "makeSIMDTernary(SIMDTernaryOp::RelaxedNmaddVecF32x4)"), + ("f64x2.relaxed_madd", "makeSIMDTernary(SIMDTernaryOp::RelaxedMaddVecF64x2)"), + ("f64x2.relaxed_nmadd", "makeSIMDTernary(SIMDTernaryOp::RelaxedNmaddVecF64x2)"), ("i8x16.laneselect", "makeSIMDTernary(SIMDTernaryOp::LaneselectI8x16)"), ("i16x8.laneselect", "makeSIMDTernary(SIMDTernaryOp::LaneselectI16x8)"), ("i32x4.laneselect", "makeSIMDTernary(SIMDTernaryOp::LaneselectI32x4)"), |