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authorThomas Lively <tlively@google.com>2022-06-07 15:46:38 -0700
committerThomas Lively <tlively@google.com>2022-06-07 15:46:38 -0700
commitb7a93cca37d2253ef36e4cc63ef38c3647404597 (patch)
tree08124eff266a067d5637bf51a5f6696008e8f82b /src/wasm/wasm-binary.cpp
parent82d82f1a4e9aa1ce1b80acbab4a95262ec7782ae (diff)
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Update relaxed SIMD instructions
Update the opcodes for all relaxed SIMD instructions and remove the unsigned dot product instructions that are no longer in the proposal.
Diffstat (limited to 'src/wasm/wasm-binary.cpp')
-rw-r--r--src/wasm/wasm-binary.cpp8
1 files changed, 0 insertions, 8 deletions
diff --git a/src/wasm/wasm-binary.cpp b/src/wasm/wasm-binary.cpp
index afad575ce..decd78852 100644
--- a/src/wasm/wasm-binary.cpp
+++ b/src/wasm/wasm-binary.cpp
@@ -5619,10 +5619,6 @@ bool WasmBinaryBuilder::maybeVisitSIMDBinary(Expression*& out, uint32_t code) {
curr = allocator.alloc<Binary>();
curr->op = DotI8x16I7x16SToVecI16x8;
break;
- case BinaryConsts::I16x8DotI8x16I7x16U:
- curr = allocator.alloc<Binary>();
- curr->op = DotI8x16I7x16UToVecI16x8;
- break;
default:
return false;
}
@@ -6101,10 +6097,6 @@ bool WasmBinaryBuilder::maybeVisitSIMDTernary(Expression*& out, uint32_t code) {
curr = allocator.alloc<SIMDTernary>();
curr->op = DotI8x16I7x16AddSToVecI32x4;
break;
- case BinaryConsts::I32x4DotI8x16I7x16AddU:
- curr = allocator.alloc<SIMDTernary>();
- curr->op = DotI8x16I7x16AddUToVecI32x4;
- break;
default:
return false;
}