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author | Thomas Lively <tlively@google.com> | 2022-06-07 15:46:38 -0700 |
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committer | Thomas Lively <tlively@google.com> | 2022-06-07 15:46:38 -0700 |
commit | b7a93cca37d2253ef36e4cc63ef38c3647404597 (patch) | |
tree | 08124eff266a067d5637bf51a5f6696008e8f82b /src/wasm/wasm-stack.cpp | |
parent | 82d82f1a4e9aa1ce1b80acbab4a95262ec7782ae (diff) | |
download | binaryen-b7a93cca37d2253ef36e4cc63ef38c3647404597.tar.gz binaryen-b7a93cca37d2253ef36e4cc63ef38c3647404597.tar.bz2 binaryen-b7a93cca37d2253ef36e4cc63ef38c3647404597.zip |
Update relaxed SIMD instructions
Update the opcodes for all relaxed SIMD instructions and remove the unsigned dot
product instructions that are no longer in the proposal.
Diffstat (limited to 'src/wasm/wasm-stack.cpp')
-rw-r--r-- | src/wasm/wasm-stack.cpp | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/src/wasm/wasm-stack.cpp b/src/wasm/wasm-stack.cpp index 8588a049f..fb24dbb01 100644 --- a/src/wasm/wasm-stack.cpp +++ b/src/wasm/wasm-stack.cpp @@ -570,9 +570,6 @@ void BinaryInstWriter::visitSIMDTernary(SIMDTernary* curr) { case DotI8x16I7x16AddSToVecI32x4: o << U32LEB(BinaryConsts::I32x4DotI8x16I7x16AddS); break; - case DotI8x16I7x16AddUToVecI32x4: - o << U32LEB(BinaryConsts::I32x4DotI8x16I7x16AddU); - break; } } @@ -1853,10 +1850,6 @@ void BinaryInstWriter::visitBinary(Binary* curr) { o << int8_t(BinaryConsts::SIMDPrefix) << U32LEB(BinaryConsts::I16x8DotI8x16I7x16S); break; - case DotI8x16I7x16UToVecI16x8: - o << int8_t(BinaryConsts::SIMDPrefix) - << U32LEB(BinaryConsts::I16x8DotI8x16I7x16U); - break; case InvalidBinary: WASM_UNREACHABLE("invalid binary op"); |