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author | Daniel Wirtz <dcode@dcode.io> | 2021-04-08 23:50:51 +0200 |
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committer | GitHub <noreply@github.com> | 2021-04-08 23:50:51 +0200 |
commit | 0efebfe68cb0e2759b88093e1811d034ef3e8a79 (patch) | |
tree | a676971fc2f671ea6817b2e218ef440d7847a827 /src/wasm | |
parent | 6921dd30dc82b3df2511def7c941f4a1a9aeeec2 (diff) | |
download | binaryen-0efebfe68cb0e2759b88093e1811d034ef3e8a79.tar.gz binaryen-0efebfe68cb0e2759b88093e1811d034ef3e8a79.tar.bz2 binaryen-0efebfe68cb0e2759b88093e1811d034ef3e8a79.zip |
Add v128.load/storeN_lane SIMD instructions to C/JS API (#3784)
Adds C/JS APIs for the SIMD instructions
* Load8LaneVec128 (was LoadLaneVec8x16)
* Load16LaneVec128 (was LoadLaneVec16x8)
* Load32LaneVec128 (was LoadLaneVec32x4)
* Load64LaneVec128 (was LoadLaneVec64x2)
* Store8LaneVec128 (was StoreLaneVec8x16)
* Store16LaneVec128 (was StoreLaneVec16x8)
* Store32LaneVec128 (was StoreLaneVec32x4)
* Store64LaneVec128 (was StoreLaneVec64x2)
Diffstat (limited to 'src/wasm')
-rw-r--r-- | src/wasm/wasm-binary.cpp | 16 | ||||
-rw-r--r-- | src/wasm/wasm-s-parser.cpp | 16 | ||||
-rw-r--r-- | src/wasm/wasm-stack.cpp | 16 | ||||
-rw-r--r-- | src/wasm/wasm-validator.cpp | 16 | ||||
-rw-r--r-- | src/wasm/wasm.cpp | 32 |
5 files changed, 48 insertions, 48 deletions
diff --git a/src/wasm/wasm-binary.cpp b/src/wasm/wasm-binary.cpp index 14a72bcb4..3ff98187f 100644 --- a/src/wasm/wasm-binary.cpp +++ b/src/wasm/wasm-binary.cpp @@ -5897,35 +5897,35 @@ bool WasmBinaryBuilder::maybeVisitSIMDLoadStoreLane(Expression*& out, size_t lanes; switch (code) { case BinaryConsts::V128Load8Lane: - op = LoadLaneVec8x16; + op = Load8LaneVec128; lanes = 16; break; case BinaryConsts::V128Load16Lane: - op = LoadLaneVec16x8; + op = Load16LaneVec128; lanes = 8; break; case BinaryConsts::V128Load32Lane: - op = LoadLaneVec32x4; + op = Load32LaneVec128; lanes = 4; break; case BinaryConsts::V128Load64Lane: - op = LoadLaneVec64x2; + op = Load64LaneVec128; lanes = 2; break; case BinaryConsts::V128Store8Lane: - op = StoreLaneVec8x16; + op = Store8LaneVec128; lanes = 16; break; case BinaryConsts::V128Store16Lane: - op = StoreLaneVec16x8; + op = Store16LaneVec128; lanes = 8; break; case BinaryConsts::V128Store32Lane: - op = StoreLaneVec32x4; + op = Store32LaneVec128; lanes = 4; break; case BinaryConsts::V128Store64Lane: - op = StoreLaneVec64x2; + op = Store64LaneVec128; lanes = 2; break; default: diff --git a/src/wasm/wasm-s-parser.cpp b/src/wasm/wasm-s-parser.cpp index a1ec5f134..8d1583059 100644 --- a/src/wasm/wasm-s-parser.cpp +++ b/src/wasm/wasm-s-parser.cpp @@ -2067,23 +2067,23 @@ SExpressionWasmBuilder::makeSIMDLoadStoreLane(Element& s, Address defaultAlign; size_t lanes; switch (op) { - case LoadLaneVec8x16: - case StoreLaneVec8x16: + case Load8LaneVec128: + case Store8LaneVec128: defaultAlign = 1; lanes = 16; break; - case LoadLaneVec16x8: - case StoreLaneVec16x8: + case Load16LaneVec128: + case Store16LaneVec128: defaultAlign = 2; lanes = 8; break; - case LoadLaneVec32x4: - case StoreLaneVec32x4: + case Load32LaneVec128: + case Store32LaneVec128: defaultAlign = 4; lanes = 4; break; - case LoadLaneVec64x2: - case StoreLaneVec64x2: + case Load64LaneVec128: + case Store64LaneVec128: defaultAlign = 8; lanes = 2; break; diff --git a/src/wasm/wasm-stack.cpp b/src/wasm/wasm-stack.cpp index 87dfe8247..31b5f1e4e 100644 --- a/src/wasm/wasm-stack.cpp +++ b/src/wasm/wasm-stack.cpp @@ -638,28 +638,28 @@ void BinaryInstWriter::visitSIMDLoad(SIMDLoad* curr) { void BinaryInstWriter::visitSIMDLoadStoreLane(SIMDLoadStoreLane* curr) { o << int8_t(BinaryConsts::SIMDPrefix); switch (curr->op) { - case LoadLaneVec8x16: + case Load8LaneVec128: o << U32LEB(BinaryConsts::V128Load8Lane); break; - case LoadLaneVec16x8: + case Load16LaneVec128: o << U32LEB(BinaryConsts::V128Load16Lane); break; - case LoadLaneVec32x4: + case Load32LaneVec128: o << U32LEB(BinaryConsts::V128Load32Lane); break; - case LoadLaneVec64x2: + case Load64LaneVec128: o << U32LEB(BinaryConsts::V128Load64Lane); break; - case StoreLaneVec8x16: + case Store8LaneVec128: o << U32LEB(BinaryConsts::V128Store8Lane); break; - case StoreLaneVec16x8: + case Store16LaneVec128: o << U32LEB(BinaryConsts::V128Store16Lane); break; - case StoreLaneVec32x4: + case Store32LaneVec128: o << U32LEB(BinaryConsts::V128Store32Lane); break; - case StoreLaneVec64x2: + case Store64LaneVec128: o << U32LEB(BinaryConsts::V128Store64Lane); break; } diff --git a/src/wasm/wasm-validator.cpp b/src/wasm/wasm-validator.cpp index 3c11f1ee3..8464a3aa9 100644 --- a/src/wasm/wasm-validator.cpp +++ b/src/wasm/wasm-validator.cpp @@ -1236,23 +1236,23 @@ void FunctionValidator::visitSIMDLoadStoreLane(SIMDLoadStoreLane* curr) { size_t lanes; Type memAlignType = Type::none; switch (curr->op) { - case LoadLaneVec8x16: - case StoreLaneVec8x16: + case Load8LaneVec128: + case Store8LaneVec128: lanes = 16; memAlignType = Type::i32; break; - case LoadLaneVec16x8: - case StoreLaneVec16x8: + case Load16LaneVec128: + case Store16LaneVec128: lanes = 8; memAlignType = Type::i32; break; - case LoadLaneVec32x4: - case StoreLaneVec32x4: + case Load32LaneVec128: + case Store32LaneVec128: lanes = 4; memAlignType = Type::i32; break; - case LoadLaneVec64x2: - case StoreLaneVec64x2: + case Load64LaneVec128: + case Store64LaneVec128: lanes = 2; memAlignType = Type::i64; break; diff --git a/src/wasm/wasm.cpp b/src/wasm/wasm.cpp index b227ff99f..5fe5eea4a 100644 --- a/src/wasm/wasm.cpp +++ b/src/wasm/wasm.cpp @@ -501,17 +501,17 @@ void SIMDLoadStoreLane::finalize() { Index SIMDLoadStoreLane::getMemBytes() { switch (op) { - case LoadLaneVec8x16: - case StoreLaneVec8x16: + case Load8LaneVec128: + case Store8LaneVec128: return 1; - case LoadLaneVec16x8: - case StoreLaneVec16x8: + case Load16LaneVec128: + case Store16LaneVec128: return 2; - case LoadLaneVec32x4: - case StoreLaneVec32x4: + case Load32LaneVec128: + case Store32LaneVec128: return 4; - case LoadLaneVec64x2: - case StoreLaneVec64x2: + case Load64LaneVec128: + case Store64LaneVec128: return 8; } WASM_UNREACHABLE("unexpected op"); @@ -519,15 +519,15 @@ Index SIMDLoadStoreLane::getMemBytes() { bool SIMDLoadStoreLane::isStore() { switch (op) { - case StoreLaneVec8x16: - case StoreLaneVec16x8: - case StoreLaneVec32x4: - case StoreLaneVec64x2: + case Store8LaneVec128: + case Store16LaneVec128: + case Store32LaneVec128: + case Store64LaneVec128: return true; - case LoadLaneVec16x8: - case LoadLaneVec32x4: - case LoadLaneVec64x2: - case LoadLaneVec8x16: + case Load16LaneVec128: + case Load32LaneVec128: + case Load64LaneVec128: + case Load8LaneVec128: return false; } WASM_UNREACHABLE("unexpected op"); |